From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Fri, 14 May 2021 05:27:51 -0700 Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq) Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4 Signed-off-by: David Abdurachmanov --- arch/riscv/Kconfig | 8 +++++ arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++ 3 files changed, 47 insertions(+) --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -566,6 +566,14 @@ config BUILTIN_DTB depends on OF default y if XIP_KERNEL +menu "CPU Power Management" + +source "drivers/cpuidle/Kconfig" + +source "drivers/cpufreq/Kconfig" + +endmenu + menu "Power management options" source "kernel/power/Kconfig" --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -30,6 +30,7 @@ i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&prci PRCI_CLK_COREPLL>; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -54,6 +55,7 @@ reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -78,6 +80,7 @@ reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -102,6 +105,7 @@ reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -126,6 +130,7 @@ reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&prci PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -84,6 +84,40 @@ label = "d4"; }; }; + + fu540_c000_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + }; + opp-999999999 { + opp-hz = /bits/ 64 <999999999>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; +&cpu1 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; +&cpu2 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; +&cpu3 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; +&cpu4 { + operating-points-v2 = <&fu540_c000_opp_table>; }; &uart0 {