// SPDX-License-Identifier: GPL-2.0-only /* * Setup for the Realtek RTL838X SoC: * Memory, Timer and Serial * * Copyright (C) 2020 B. Koblitz * based on the original BSP by * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mach-rtl83xx.h" extern struct rtl83xx_soc_info soc_info; void __init plat_mem_setup(void) { void *dtb; set_io_port_base(KSEG1); dtb = get_fdt(); if (!dtb) panic("no dtb found"); /* * Load the devicetree. This causes the chosen node to be * parsed resulting in our memory appearing */ __dt_setup_arch(dtb); } void plat_time_init_fallback(void) { struct device_node *np; u32 freq = 500000000; np = of_find_node_by_name(NULL, "cpus"); if (!np) { pr_err("Missing 'cpus' DT node, using default frequency."); } else { if (of_property_read_u32(np, "frequency", &freq) < 0) pr_err("No 'frequency' property in DT, using default."); else pr_info("CPU frequency from device tree: %dMHz", freq / 1000000); of_node_put(np); } mips_hpt_frequency = freq / 2; } void __init plat_time_init(void) { /* * Initialization routine resembles generic MIPS plat_time_init() with * lazy error handling. The final fallback is only needed until we have * converted all device trees to new clock syntax. */ struct device_node *np; struct clk *clk; of_clk_init(NULL); mips_hpt_frequency = 0; np = of_get_cpu_node(0, NULL); if (!np) { pr_err("Failed to get CPU node\n"); } else { clk = of_clk_get(np, 0); if (IS_ERR(clk)) { pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); } else { mips_hpt_frequency = clk_get_rate(clk) / 2; clk_put(clk); } } if (!mips_hpt_frequency) plat_time_init_fallback(); timer_probe(); } void __init arch_init_irq(void) { irqchip_init(); }