// SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; #include "rtl930x.dtsi" #include #include #include / { compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc"; model = "Zyxel XGS1250-12 Switch"; aliases { led-boot = &led_pwr_sys; led-failsafe = &led_pwr_sys; led-running = &led_pwr_sys; led-upgrade = &led_pwr_sys; }; keys { compatible = "gpio-keys"; mode { label = "reset"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; linux,code = ; }; }; /* i2c of the SFP cage: port 12 */ i2c0: i2c-rtl9300 { compatible = "realtek,rtl9300-i2c"; reg = <0x1b00036c 0x3c>; #address-cells = <1>; #size-cells = <0>; sda-pin = <10>; scl-pin = <8>; clock-frequency = <100000>; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinmux_disable_sys_led>; led_pwr_sys: led-0 { label = "green:power"; color = ; function = LED_FUNCTION_POWER; gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; }; }; sfp0: sfp-p12 { compatible = "sff,sfp"; i2c-bus = <&i2c0>; los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; led_set: led_set@0 { compatible = "realtek,rtl9300-leds"; active-low; led_set0 = <0x0000 0xffff 0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G) // (5G, 10/100) (10G, 5G, 2.5G) led_set2 = <0x0000 0xffff 0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit }; }; &spi0 { status = "okay"; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x0 0xe0000>; read-only; }; partition@e0000 { label = "u-boot-env"; reg = <0xe0000 0x10000>; }; partition@f0000 { label = "u-boot-env2"; reg = <0xf0000 0x10000>; read-only; }; partition@100000 { label = "jffs"; reg = <0x100000 0x100000>; }; partition@200000 { label = "jffs2"; reg = <0x200000 0x100000>; }; partition@b300000 { label = "firmware"; reg = <0x300000 0xce0000>; compatible = "openwrt,uimage", "denx,uimage"; openwrt,ih-magic = <0x93001250>; }; partition@fe0000 { label = "log"; reg = <0xfe0000 0x20000>; }; }; }; }; ðernet0 { mdio: mdio-bus { compatible = "realtek,rtl838x-mdio"; regmap = <ðernet0>; #address-cells = <1>; #size-cells = <0>; /* External RTL8218D PHY */ phy0: ethernet-phy@0 { reg = <0>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 0>; sds = < 2 >; // Disabled because we do not know how to bring up again // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@1 { reg = <1>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 1>; }; phy2: ethernet-phy@2 { reg = <2>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 2>; }; phy3: ethernet-phy@3 { reg = <3>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 3>; }; phy4: ethernet-phy@4 { reg = <4>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 4>; }; phy5: ethernet-phy@5 { reg = <5>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 5>; }; phy6: ethernet-phy@6 { reg = <6>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 6>; }; phy7: ethernet-phy@7 { reg = <7>; compatible = "ethernet-phy-ieee802.3-c22"; rtl9300,smi-address = <0 7>; }; /* External Aquantia 113C PHYs */ phy24: ethernet-phy@24 { reg = <24>; compatible = "ethernet-phy-ieee802.3-c45"; rtl9300,smi-address = <1 8>; sds = < 6 >; // Disabled because we do not know how to bring up again // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; phy25: ethernet-phy@25 { reg = <25>; compatible = "ethernet-phy-ieee802.3-c45"; rtl9300,smi-address = <2 8>; sds = < 7 >; // Disabled because we do not know how to bring up again // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; phy26: ethernet-phy@26 { reg = <26>; compatible = "ethernet-phy-ieee802.3-c45"; rtl9300,smi-address = <3 8>; sds = < 8 >; // Disabled because we do not know how to bring up again // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; /* SFP Ports */ phy27: ethernet-phy@27 { compatible = "ethernet-phy-ieee802.3-c22"; phy-is-integrated; reg = <27>; rtl9300,smi-address = <4 0>; sds = < 9 >; }; }; }; &switch0 { ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; phy-handle = <&phy0>; phy-mode = "xgmii"; led-set = <0>; }; port@1 { reg = <1>; label = "lan2"; phy-handle = <&phy1>; phy-mode = "xgmii"; led-set = <0>; }; port@2 { reg = <2>; label = "lan3"; phy-handle = <&phy2>; phy-mode = "xgmii"; led-set = <0>; }; port@3 { reg = <3>; label = "lan4"; phy-handle = <&phy3>; phy-mode = "xgmii"; led-set = <0>; }; port@4 { reg = <4>; label = "lan5"; phy-handle = <&phy4>; phy-mode = "xgmii"; led-set = <0>; }; port@5 { reg = <5>; label = "lan6"; phy-handle = <&phy5>; phy-mode = "xgmii"; led-set = <0>; }; port@6 { reg = <6>; label = "lan7"; phy-handle = <&phy6>; phy-mode = "xgmii"; led-set = <0>; }; port@7 { reg = <7>; label = "lan8"; phy-handle = <&phy7>; phy-mode = "xgmii"; led-set = <0>; }; port@24 { reg = <24>; label = "lan9"; phy-mode = "usxgmii"; phy-handle = <&phy24>; led-set = <1>; }; port@25 { reg = <25>; label = "lan10"; phy-mode = "usxgmii"; phy-handle = <&phy25>; led-set = <1>; }; port@26 { reg = <26>; label = "lan11"; phy-mode = "usxgmii"; phy-handle = <&phy26>; led-set = <1>; }; port@27 { reg = <27>; label = "lan12"; phy-mode = "10gbase-r"; phy-handle = <&phy27>; sfp = <&sfp0>; led-set = <2>; fixed-link { speed = <10000>; full-duplex; pause; }; }; port@28 { ethernet = <ðernet0>; reg = <28>; phy-mode = "internal"; fixed-link { speed = <10000>; full-duplex; }; }; }; };