// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "rtl839x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "netgear,gs750e", "realtek,rtl8393-soc";
	model = "Netgear GS750E";

	aliases {
		label-mac-device = &ethernet0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x8000000>;
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
	};

	virtual_flash {
		compatible = "mtd-concat";

		devices = <&fwconcat0>, <&fwconcat1>, <&fwconcat2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "firmware";
				reg = <0x0 0x760000>;
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,ih-magic = <0x174e4741>;
			};
		};
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x80000>;
				read-only;
			};

			partition@80000 {
				label = "u-boot-env";
				reg = <0x80000 0x10000>;
				read-only;
			};

			partition@90000 {
				label = "u-boot-env2";
				reg = <0x90000 0x10000>;
				read-only;
			};

			fwconcat1: partition@a0000 {
				label = "jffs2_cfg";
				reg = <0xa0000 0x80000>;
			};

			fwconcat2: partition@120000 {
				label = "jffs2_log";
				reg = <0x120000 0x80000>;
			};

			fwconcat0: partition@1a0000 {
				label = "runtime";
				reg = <0x1a0000 0x660000>;
			};
		};
	};
};

&ethernet0 {
	mdio: mdio-bus {
		compatible = "realtek,rtl838x-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;

		/* External phy RTL8218B #1 */
		EXTERNAL_PHY(0)
		EXTERNAL_PHY(1)
		EXTERNAL_PHY(2)
		EXTERNAL_PHY(3)
		EXTERNAL_PHY(4)
		EXTERNAL_PHY(5)
		EXTERNAL_PHY(6)
		EXTERNAL_PHY(7)

		/* External phy RTL8218B #2 */
		EXTERNAL_PHY(8)
		EXTERNAL_PHY(9)
		EXTERNAL_PHY(10)
		EXTERNAL_PHY(11)
		EXTERNAL_PHY(12)
		EXTERNAL_PHY(13)
		EXTERNAL_PHY(14)
		EXTERNAL_PHY(15)

		/* External phy RTL8218B #3 */
		EXTERNAL_PHY(16)
		EXTERNAL_PHY(17)
		EXTERNAL_PHY(18)
		EXTERNAL_PHY(19)
		EXTERNAL_PHY(20)
		EXTERNAL_PHY(21)
		EXTERNAL_PHY(22)
		EXTERNAL_PHY(23)

		/* External phy RTL8218B #4 */
		EXTERNAL_PHY(24)
		EXTERNAL_PHY(25)
		EXTERNAL_PHY(26)
		EXTERNAL_PHY(27)
		EXTERNAL_PHY(28)
		EXTERNAL_PHY(29)
		EXTERNAL_PHY(30)
		EXTERNAL_PHY(31)

		/* External phy RTL8218B #5 */
		EXTERNAL_PHY(32)
		EXTERNAL_PHY(33)
		EXTERNAL_PHY(34)
		EXTERNAL_PHY(35)
		EXTERNAL_PHY(36)
		EXTERNAL_PHY(37)
		EXTERNAL_PHY(38)
		EXTERNAL_PHY(39)

		/* External phy RTL8218B #6 */
		EXTERNAL_PHY(40)
		EXTERNAL_PHY(41)
		EXTERNAL_PHY(42)
		EXTERNAL_PHY(43)
		EXTERNAL_PHY(44)
		EXTERNAL_PHY(45)
		EXTERNAL_PHY(46)
		EXTERNAL_PHY(47)

		/* RTL8393 Internal SerDes */
		INTERNAL_PHY(48)
		INTERNAL_PHY(49)
	};
};

&switch0 {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT(0, 1, qsgmii)
		SWITCH_PORT(1, 2, qsgmii)
		SWITCH_PORT(2, 3, qsgmii)
		SWITCH_PORT(3, 4, qsgmii)
		SWITCH_PORT(4, 5, qsgmii)
		SWITCH_PORT(5, 6, qsgmii)
		SWITCH_PORT(6, 7, qsgmii)
		SWITCH_PORT(7, 8, qsgmii)

		SWITCH_PORT(8, 9, qsgmii)
		SWITCH_PORT(9, 0, qsgmii)
		SWITCH_PORT(10, 11, qsgmii)
		SWITCH_PORT(11, 12, qsgmii)
		SWITCH_PORT(12, 13, qsgmii)
		SWITCH_PORT(13, 14, qsgmii)
		SWITCH_PORT(14, 15, qsgmii)
		SWITCH_PORT(15, 16, qsgmii)

		SWITCH_PORT(16, 17, qsgmii)
		SWITCH_PORT(17, 18, qsgmii)
		SWITCH_PORT(18, 19, qsgmii)
		SWITCH_PORT(19, 20, qsgmii)
		SWITCH_PORT(20, 21, qsgmii)
		SWITCH_PORT(21, 22, qsgmii)
		SWITCH_PORT(22, 23, qsgmii)
		SWITCH_PORT(23, 24, qsgmii)

		SWITCH_PORT(24, 25, qsgmii)
		SWITCH_PORT(25, 26, qsgmii)
		SWITCH_PORT(26, 27, qsgmii)
		SWITCH_PORT(27, 28, qsgmii)
		SWITCH_PORT(28, 29, qsgmii)
		SWITCH_PORT(29, 30, qsgmii)
		SWITCH_PORT(30, 31, qsgmii)
		SWITCH_PORT(31, 32, qsgmii)

		SWITCH_PORT(32, 33, qsgmii)
		SWITCH_PORT(33, 34, qsgmii)
		SWITCH_PORT(34, 35, qsgmii)
		SWITCH_PORT(35, 36, qsgmii)
		SWITCH_PORT(36, 37, qsgmii)
		SWITCH_PORT(37, 38, qsgmii)
		SWITCH_PORT(38, 39, qsgmii)
		SWITCH_PORT(39, 40, qsgmii)

		SWITCH_PORT(40, 41, qsgmii)
		SWITCH_PORT(41, 42, qsgmii)
		SWITCH_PORT(42, 43, qsgmii)
		SWITCH_PORT(43, 44, qsgmii)
		SWITCH_PORT(44, 45, qsgmii)
		SWITCH_PORT(45, 46, qsgmii)
		SWITCH_PORT(46, 47, qsgmii)
		SWITCH_PORT(47, 48, qsgmii)

		/* SFP cages */
		SWITCH_SFP_PORT(48, 49, sgmii)
		SWITCH_SFP_PORT(49, 50, sgmii)

		/* CPU-Port */
		port@52 {
			ethernet = <&ethernet0>;
			reg = <52>;
			phy-mode = "qsgmii";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};