--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -21,6 +21,10 @@
 		stdout-path = "serial2:115200n8";
 	};
 
+	memory {
+		reg = <0 0x80000000 0 0x20000000>;
+	};
+
 	cpus {
 		cpu@0 {
 			proc-supply = <&mt6323_vproc_reg>;
@@ -103,6 +107,10 @@
 		device_type = "memory";
 		reg = <0 0x80000000 0 0x40000000>;
 	};
+
+	mt7530: switch@0 {
+		compatible = "mediatek,mt7530";
+	};
 };
 
 &cir {
@@ -130,11 +138,24 @@
 		};
 	};
 
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "rgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			pause;
+		};
+	};
+
 	mdio: mdio-bus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-
-		switch@0 {
+	};
+};
+		&mt7530 {
 			compatible = "mediatek,mt7530";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -144,6 +165,8 @@
 			core-supply = <&mt6323_vpa_reg>;
 			io-supply = <&mt6323_vemc3v3_reg>;
 
+			dsa,mii-bus = <&mdio>;
+
 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -152,29 +175,46 @@
 				port@0 {
 					reg = <0>;
 					label = "wan";
+					cpu = <&cpu_port1>;
 				};
 
 				port@1 {
 					reg = <1>;
 					label = "lan0";
+					cpu = <&cpu_port0>;
 				};
 
 				port@2 {
 					reg = <2>;
 					label = "lan1";
+					cpu = <&cpu_port0>;
 				};
 
 				port@3 {
 					reg = <3>;
 					label = "lan2";
+					cpu = <&cpu_port0>;
 				};
 
 				port@4 {
 					reg = <4>;
 					label = "lan3";
+					cpu = <&cpu_port0>;
 				};
 
-				port@6 {
+				cpu_port1: port@5 {
+					reg = <5>;
+					label = "cpu";
+					ethernet = <&gmac1>;
+					phy-mode = "rgmii";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+
+				cpu_port0: port@6 {
 					reg = <6>;
 					label = "cpu";
 					ethernet = <&gmac0>;
@@ -187,8 +227,6 @@
 				};
 			};
 		};
-	};
-};
 
 &i2c0 {
 	pinctrl-names = "default";
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -326,6 +326,7 @@
 			     "syscon";
 		reg = <0 0x10209000 0 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	rng: rng@1020f000 {