From 269a71c81438604d27f01ec703daa7f5e3f39e8b Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Sun, 15 Jun 2014 00:48:18 -0500 Subject: [PATCH 159/182] arm: ipq8064: Add USB3 DT information This patch fleshes out the USB3 specific information for the IPQ8064 platform. Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 29 ++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 90 ++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 4062eb6..2b2d63c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -160,5 +160,34 @@ pinctrl-0 = <&nand_pins>; pinctrl-names = "default"; }; + + tcsr@1a400000 { + status = "ok"; + qcom,usb-ctrl-select = ; + }; + + phy@100f8800 { /* USB3 port 1 HS phy */ + status = "ok"; + }; + + phy@100f8830 { /* USB3 port 1 SS phy */ + status = "ok"; + }; + + phy@110f8800 { /* USB3 port 0 HS phy */ + status = "ok"; + }; + + phy@110f8830 { /* USB3 port 0 SS phy */ + status = "ok"; + }; + + usb30@0 { + status = "ok"; + }; + + usb30@1 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index d9fce15..6be6ac9 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { model = "Qualcomm IPQ8064"; @@ -402,5 +403,94 @@ status = "disabled"; }; + + tcsr: tcsr@1a400000 { + compatible = "qcom,tcsr"; + reg = <0x1a400000 0x100>; + + status = "disabled"; + }; + + hs_phy_1: phy@100f8800 { + compatible = "qcom,dwc3-hsphy"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "utmi"; + + status = "disabled"; + }; + + ss_phy_1: phy@100f8830 { + compatible = "qcom,dwc3-ssphy"; + reg = <0x100f8830 0x30>; + + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + + status = "disabled"; + }; + + hs_phy_0: phy@110f8800 { + compatible = "qcom,dwc3-hsphy"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "utmi"; + + status = "disabled"; + }; + + ss_phy_0: phy@110f8830 { + compatible = "qcom,dwc3-ssphy"; + reg = <0x110f8830 0x30>; + + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + + status = "disabled"; + }; + + usb3_0: usb30@0 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + status = "disabled"; + + dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <0 110 0x4>; + usb-phy = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + }; + }; + + usb3_1: usb30@1 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + status = "disabled"; + + dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <0 205 0x4>; + usb-phy = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + }; + }; }; }; -- 1.7.10.4