From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001 From: Ram Chandra Jangir Date: Tue, 9 May 2017 11:45:00 +0530 Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits GPIO_PULL bits configurations in TLMM_GPIO_CFG register differs for IPQ40xx from rest of the other qcom SoC's. This change add support to configure the msm_gpio_pull bits for ipq40xx, It is required to fix the proper configurations of gpio-pull bits for nand pins mux. IPQ40xx SoC: 2'b10: Internal pull up enable. 2'b11: Unsupport For other SoC's: 2'b10: Keeper 2'b11: Pull-Up Signed-off-by: Ram Chandra Jangir --- drivers/pinctrl/qcom/pinctrl-apq8064.c | 1 + drivers/pinctrl/qcom/pinctrl-apq8084.c | 1 + drivers/pinctrl/qcom/pinctrl-ipq4019.c | 8 ++++++++ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 1 + drivers/pinctrl/qcom/pinctrl-mdm9615.c | 1 + drivers/pinctrl/qcom/pinctrl-msm.c | 21 ++++++++------------- drivers/pinctrl/qcom/pinctrl-msm.h | 19 +++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm8660.c | 1 + drivers/pinctrl/qcom/pinctrl-msm8916.c | 1 + drivers/pinctrl/qcom/pinctrl-msm8960.c | 1 + drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1 + 11 files changed, 43 insertions(+), 13 deletions(-) --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data .groups = apq8064_groups, .ngroups = ARRAY_SIZE(apq8064_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int apq8064_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data .groups = apq8084_groups, .ngroups = ARRAY_SIZE(apq8084_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int apq8084_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019 PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), }; +static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = { + .no_pull = 0, + .pull_down = 1, + .keeper = 0, + .pull_up = 2, +}; + static const struct msm_pinctrl_soc_data ipq4019_pinctrl = { .pins = ipq4019_pins, .npins = ARRAY_SIZE(ipq4019_pins), @@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data .groups = ipq4019_groups, .ngroups = ARRAY_SIZE(ipq4019_groups), .ngpios = 100, + .gpio_pull = &ipq4019_gpio_pull, }; static int ipq4019_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data .groups = ipq8064_groups, .ngroups = ARRAY_SIZE(ipq8064_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int ipq8064_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data .groups = mdm9615_groups, .ngroups = ARRAY_SIZE(mdm9615_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int mdm9615_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin return 0; } -#define MSM_NO_PULL 0 -#define MSM_PULL_DOWN 1 -#define MSM_KEEPER 2 -#define MSM_PULL_UP 3 - static unsigned msm_regval_to_drive(u32 val) { return (val + 1) * 2; @@ -238,16 +233,16 @@ static int msm_config_group_get(struct p /* Convert register value to pinconf value */ switch (param) { case PIN_CONFIG_BIAS_DISABLE: - arg = arg == MSM_NO_PULL; + arg = arg == pctrl->soc->gpio_pull->no_pull; break; case PIN_CONFIG_BIAS_PULL_DOWN: - arg = arg == MSM_PULL_DOWN; + arg = arg == pctrl->soc->gpio_pull->pull_down; break; case PIN_CONFIG_BIAS_BUS_HOLD: - arg = arg == MSM_KEEPER; + arg = arg == pctrl->soc->gpio_pull->keeper; break; case PIN_CONFIG_BIAS_PULL_UP: - arg = arg == MSM_PULL_UP; + arg = arg == pctrl->soc->gpio_pull->pull_up; break; case PIN_CONFIG_DRIVE_STRENGTH: arg = msm_regval_to_drive(arg); @@ -304,16 +299,16 @@ static int msm_config_group_set(struct p /* Convert pinconf values to register values */ switch (param) { case PIN_CONFIG_BIAS_DISABLE: - arg = MSM_NO_PULL; + arg = pctrl->soc->gpio_pull->no_pull; break; case PIN_CONFIG_BIAS_PULL_DOWN: - arg = MSM_PULL_DOWN; + arg = pctrl->soc->gpio_pull->pull_down; break; case PIN_CONFIG_BIAS_BUS_HOLD: - arg = MSM_KEEPER; + arg = pctrl->soc->gpio_pull->keeper; break; case PIN_CONFIG_BIAS_PULL_UP: - arg = MSM_PULL_UP; + arg = pctrl->soc->gpio_pull->pull_up; break; case PIN_CONFIG_DRIVE_STRENGTH: /* Check for invalid values */ --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -98,6 +98,16 @@ struct msm_pingroup { }; /** + * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor + */ +struct msm_pinctrl_gpio_pull { + unsigned no_pull; + unsigned pull_down; + unsigned keeper; + unsigned pull_up; +}; + +/** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. * @npins: The number of entries in @pins. @@ -106,6 +116,7 @@ struct msm_pingroup { * @groups: An array describing all pin groups the pin SoC supports. * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. + * @gpio_pull_val: The pull value bit field descriptor. */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data { const struct msm_pingroup *groups; unsigned ngroups; unsigned ngpios; + const struct msm_pinctrl_gpio_pull *gpio_pull; +}; + +static const struct msm_pinctrl_gpio_pull msm_gpio_pull = { + .no_pull = 0, + .pull_down = 1, + .keeper = 2, + .pull_up = 3, }; int msm_pinctrl_probe(struct platform_device *pdev, --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data .groups = msm8660_groups, .ngroups = ARRAY_SIZE(msm8660_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int msm8660_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data .groups = msm8916_groups, .ngroups = ARRAY_SIZE(msm8916_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int msm8916_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data .groups = msm8960_groups, .ngroups = ARRAY_SIZE(msm8960_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int msm8960_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data .groups = msm8x74_groups, .ngroups = ARRAY_SIZE(msm8x74_groups), .ngpios = NUM_GPIO_PINGROUPS, + .gpio_pull = &msm_gpio_pull, }; static int msm8x74_pinctrl_probe(struct platform_device *pdev)