From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Mon, 23 Jul 2018 09:10:35 +0200 Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq support This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock Signed-off-by: John Crispin --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 8 deletions(-) --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -41,14 +41,7 @@ reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 666000 1100000 - >; - clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@1 { @@ -61,6 +54,7 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@2 { @@ -73,6 +67,7 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { @@ -85,6 +80,7 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points-v2 = <&cpu0_opp_table>; }; L2: l2-cache { @@ -94,6 +90,32 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-48000000 { + opp-hz = /bits/ 64 <48000000>; + clock-latency-ns = <256000>; + opp-microvolt = <1100000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <256000>; + opp-microvolt = <1100000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <256000>; + opp-microvolt = <1100000>; + }; + opp-716000000 { + opp-hz = /bits/ 64 <716000000>; + clock-latency-ns = <256000>; + opp-microvolt = <1100000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts =