From 13ad5ccc093ff448b99ac7e138e91e78796adb48 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Thu, 14 Oct 2021 00:39:12 +0200 Subject: dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -45,6 +45,16 @@ A CPU port node has the following option Mostly used in qca8327 with CPU port 0 set to sgmii. - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX + chain along with Signal Detection. + This should NOT be enabled for qca8327. If enabled with + qca8327 the sgmii port won't correctly init and an err + is printed. + This can be required for qca8337 switch with revision 2. + A warning is displayed when used with revision greater + 2. + With CPU port set to sgmii and qca8337 it is advised + to set this unless a communication problem is observed. For QCA8K the 'fixed-link' sub-node supports only the following properties: