From ae5d39403c61f4ed691a0a8d94673210475242be Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 15 Aug 2017 16:47:18 -0700 Subject: [PATCH 204/454] drm/vc4: Move the DSI clock divider workaround closer to the clock call. We want the adjusted_mode->clock to be the actual clock we're expecting to program, so that consumers see the right values for clock and vrefresh. Signed-off-by: Eric Anholt Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net Reviewed-by: Boris Brezillon (cherry picked from commit d409eeafa9ba1c0f2eb75a2619fc787808a545e4) --- drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -864,11 +864,7 @@ static bool vc4_dsi_encoder_mode_fixup(s pll_clock = parent_rate / divider; pixel_clock_hz = pll_clock / dsi->divider; - /* Round up the clk_set_rate() request slightly, since - * PLLD_DSI1 is an integer divider and its rate selection will - * never round up. - */ - adjusted_mode->clock = pixel_clock_hz / 1000 + 1; + adjusted_mode->clock = pixel_clock_hz / 1000; /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / @@ -906,7 +902,11 @@ static void vc4_dsi_encoder_enable(struc vc4_dsi_dump_regs(dsi); } - phy_clock = pixel_clock_hz * dsi->divider; + /* Round up the clk_set_rate() request slightly, since + * PLLD_DSI1 is an integer divider and its rate selection will + * never round up. + */ + phy_clock = (pixel_clock_hz + 1000) * dsi->divider; ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); if (ret) { dev_err(&dsi->pdev->dev,