From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 17 Jun 2020 12:50:39 +0200 Subject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6368-reset.h --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi @@ -70,6 +70,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, --- /dev/null +++ b/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */