From 9d71b0d4e30692d0d186352b494ef4e70234ca7c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Mar 2022 17:09:41 +0100 Subject: [PATCH] drm/vc4: Make sure we don't end up with a core clock too high Following the clock rate range improvements to the clock framework, trying to set a disjoint range on a clock will now result in an error. Thus, we can't set a minimum rate higher than the maximum reported by the firmware, or clk_set_min_rate() will fail. Thus we need to clamp the rate we are about to ask for to the maximum rate possible on that clock. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_kms.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -354,6 +354,7 @@ static void vc4_atomic_commit_tail(struc struct vc4_hvs_state *new_hvs_state; struct drm_crtc *crtc; struct vc4_hvs_state *old_hvs_state; + unsigned long max_clock_rate = clk_get_max_rate(hvs->core_clk); unsigned int channel; int i; @@ -397,8 +398,8 @@ static void vc4_atomic_commit_tail(struc if (vc4->hvs && vc4->hvs->hvs5) { unsigned long state_rate = max(old_hvs_state->core_clock_rate, new_hvs_state->core_clock_rate); - unsigned long core_rate = max_t(unsigned long, - 500000000, state_rate); + unsigned long core_rate = clamp_t(unsigned long, state_rate, + 500000000, max_clock_rate); WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); } @@ -427,10 +428,13 @@ static void vc4_atomic_commit_tail(struc drm_atomic_helper_cleanup_planes(dev, state); if (vc4->hvs && vc4->hvs->hvs5) { - drm_dbg(dev, "Running the core clock at %lu Hz\n", - new_hvs_state->core_clock_rate); + unsigned long core_rate = min_t(unsigned long, + max_clock_rate, + new_hvs_state->core_clock_rate); + + drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate); - WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate)); + WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); drm_dbg(dev, "Core clock actual rate: %lu Hz\n", clk_get_rate(hvs->core_clk));