From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 25 Jun 2018 15:52:02 +0200 Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc With the driver being converted from platform_data to pure OF, we need to also add some docs. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: John Crispin --- .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt @@ -0,0 +1,42 @@ +* Qualcomm Atheros AR724X PCI express root complex + +Required properties: +- compatible: should contain "qcom,ar7240-pci" to identify the core. +- reg: Should contain the register ranges as listed in the reg-names property. +- reg-names: Definition: Must include the following entries + - "crp_base" Configuration registers + - "ctrl_base" Control registers + - "cfg_base" IO Memory +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the PCI memory and I/O regions +- interrupt-map-mask and interrupt-map: standard PCI + properties to define the mapping of the PCIe interface to interrupt + numbers. +- #interrupt-cells: set to <1> +- interrupt-parent: phandle to the MIPS IRQ controller + +Optional properties: +- interrupt-controller: define to enable the builtin IRQ cascade. + +* Example for qca9557 + pcie-controller@180c0000 { + compatible = "qcom,ar7240-pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + reg = <0x180c0000 0x1000>, + <0x180f0000 0x100>, + <0x14000000 0x1000>; + reg-names = "crp_base", "ctrl_base", "cfg_base"; + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; + interrupt-parent = <&intc2>; + interrupts = <1>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 1>; + interrupt-map = <0 0 0 0 &pcie0 0>; + };