--- /dev/null +++ b/configs/mt7981_cmcc_rax3000m-emmc_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-emmc" +CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-emmc_env" +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-emmc.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_BOOTDELAY=30 +CONFIG_AUTOBOOT_MENU_SHOW=y +CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_FIT=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7981> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ENV_READMEM=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FDT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_HASH=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_PWM=y +CONFIG_CMD_SMC=y +CONFIG_CMD_TFTPBOOT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_USB=y +CONFIG_CMD_UUID=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DM_MMC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_USB=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_SCSI=y +CONFIG_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_PHY_FIXED=y +CONFIG_MTK_AHCI=y +CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_MMC=y +CONFIG_MMC_DEFAULT_DEV=1 +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SUPPORTS_TUNING=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_MTK=y +CONFIG_LZO=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y +CONFIG_RANDOM_UUID=y +CONFIG_REGEX=y +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_OFFSET_REDUND=0x440000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE_REDUND=0x40000 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_HEXDUMP=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_CMD_SF=y +CONFIG_LMB_MAX_REGIONS=64 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7981_cmcc_rax3000m-nand_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-nand" +CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-nand_env" +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-nand.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_BOOTDELAY=30 +CONFIG_AUTOBOOT_MENU_SHOW=y +CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_FIT=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7981> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ENV_READMEM=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FDT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_HASH=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_PWM=y +CONFIG_CMD_SMC=y +CONFIG_CMD_TFTPBOOT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y +CONFIG_CMD_UBIFS=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_UUID=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DM_MTD=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_SCSI=y +CONFIG_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_PHY_FIXED=y +CONFIG_MTK_AHCI=y +CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PCI=y +# CONFIG_MMC is not set +# CONFIG_DM_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPI_NAND=y +CONFIG_MTK_SPI_NAND_MTD=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_MTK=y +CONFIG_LZO=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y +CONFIG_RANDOM_UUID=y +CONFIG_REGEX=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="ubi" +CONFIG_ENV_SIZE=0x1f000 +CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_HEXDUMP=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTK_SPIM=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_LMB_MAX_REGIONS=64 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981-cmcc-rax3000m.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +/dts-v1/; +#include "mt7981.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "CMCC RAX3000M"; + compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + button-mesh { + label = "mesh"; + linux,code = ; + linux,input-type = ; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "green:status"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "blue:status"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "red:status"; + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + }; +}; + +&uart0 { + mediatek,force-highspeed; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; --- /dev/null +++ b/arch/arm/dts/mt7981-cmcc-rax3000m-emmc.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +#include "mt7981-cmcc-rax3000m.dtsi" + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + max-frequency = <26000000>; + bus-width = <8>; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&pinctrl { + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = ; + bias-pull-down = ; + }; + conf-rst { + pins = "PWM0"; + drive-strength = ; + bias-pull-up = ; + }; + }; +}; --- /dev/null +++ b/arch/arm/dts/mt7981-cmcc-rax3000m-nand.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +#include "mt7981-cmcc-rax3000m.dtsi" + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "orig-env"; + reg = <0x100000 0x80000>; + }; + + partition@160000 { + label = "factory"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7200000>; + }; + }; + }; +}; --- /dev/null +++ b/cmcc_rax3000m-emmc_env @@ -0,0 +1,55 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x46000000 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 +bootargs=root=/dev/mmcblk0p65 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi +bootconf=config-1#mt7981b-cmcc-rax3000m-emmc +bootdelay=0 +bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb +bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-preloader.bin +bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-bl31-uboot.fip +bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb +bootled_pwr=red:status +bootled_rec=blue:status +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 +bootmenu_default=0 +bootmenu_delay=0 +bootmenu_title= ( ( ( OpenWrt ) ) ) [eMMC] +bootmenu_0=Initialize environment.=run _firstboot +bootmenu_0d=Run default boot command.=run boot_default +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return +bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return +bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return +bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return +bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return +bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return +bootmenu_8=Reboot.=reset +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever +boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off +boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off +boot_emmc=run boot_production ; run boot_recovery +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size +mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 +part_default=production +part_recovery=recovery +reset_factory=eraseenv && reset +emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol +emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol +emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 +emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 +emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol +emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- /dev/null +++ b/cmcc_rax3000m-nand_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x46000000 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 +bootconf=config-1#mt7981b-cmcc-rax3000m-nand +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi +bootdelay=0 +bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb +bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-nand-preloader.bin +bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-nand-bl31-uboot.fip +bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb +bootled_pwr=red:status +bootled_rec=blue:status +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 +bootmenu_default=0 +bootmenu_delay=0 +bootmenu_title= ( ( ( OpenWrt ) ) ) [SPI-NAND] +bootmenu_0=Initialize environment.=run _firstboot +bootmenu_0d=Run default boot command.=run boot_default +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return +bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return +bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return +bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return +bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return +bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return +bootmenu_8=Reboot.=reset +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off +boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off +boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 +part_default=production +part_recovery=recovery +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr +ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data +ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize +ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"