From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Mon, 13 Jun 2016 17:29:59 +0530 Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings DDR timigs displayed for LS1012A were half of true value. Updated DDR value to 1000 MT/s. Signed-off-by: Pratiyush Mohan Srivastava --- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 63e5bed..a4dde5b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } - if (ver == SVR_LS1012) + if (ver == SVR_LS1012){ sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - + sys_info->freq_ddrbus *=2; + } #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN -- 1.7.9.5