From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 2 May 2016 18:28:16 +0530 Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence Current DDR init code uses lots of delay. Use wait for bit clear instead of delays. Signed-off-by: Calvin Johnson Signed-off-by: Prabhakar Kushwaha --- board/freescale/ls1012aqds/ls1012aqds.c | 67 +++++++++++++++++-------------- board/freescale/ls1012ardb/ls1012ardb.c | 54 +++++++++++-------------- 2 files changed, 60 insertions(+), 61 deletions(-) diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 6d5fef8..5cb225f 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -28,6 +28,20 @@ DECLARE_GLOBAL_DATA_PTR; +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + int checkboard(void) { puts("Board: LS1012AQDS\n"); @@ -44,7 +58,7 @@ void mmdc_init(void) out_be32(&mmdc->mdscr, 0x00008000); /* configure timing parms */ - out_be32(&mmdc->mdotc, 0x12554000); + out_be32(&mmdc->mdotc, 0x12554000); out_be32(&mmdc->mdcfg0, 0xbabf7954); out_be32(&mmdc->mdcfg1, 0xff328f64); out_be32(&mmdc->mdcfg2, 0x01ff00db); @@ -56,7 +70,7 @@ void mmdc_init(void) out_be32(&mmdc->mpodtctrl, 0x0000022a); /* out of reset delays */ - out_be32(&mmdc->mdor, 0x00bf1023); + out_be32(&mmdc->mdor, 0x00bf1023); /* physical parms */ out_be32(&mmdc->mdctl, 0x05180000); @@ -73,69 +87,60 @@ void mmdc_init(void) /* dram init sequence: ZQCL */ out_be32(&mmdc->mdscr, 0x04008040); - out_be32(&mmdc->mpzqhwctrl, 0xa1390003); - - mdelay(100); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000); /* Calibrations now: wr lvl */ out_be32(&mmdc->mdscr, 0x00848031); out_be32(&mmdc->mdscr, 0x00008200); - out_be32(&mmdc->mpwlgcr, 0x00000001); + set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001); - mdelay(100); + mdelay(1); out_be32(&mmdc->mdscr, 0x00048031); out_be32(&mmdc->mdscr, 0x00008000); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); + mdelay(1); /* Calibrations now: Read DQS gating calibration */ out_be32(&mmdc->mdscr, 0x04008050); out_be32(&mmdc->mdscr, 0x00048033); out_be32(&mmdc->mppdcmpr2, 0x00000001); out_be32(&mmdc->mprddlctl, 0x40404040); - out_be32(&mmdc->mpdgctrl0, 0x10000000); - - mdelay(100); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000); out_be32(&mmdc->mdscr, 0x00008033); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); /* Calibrations now: Read calibration */ out_be32(&mmdc->mdscr, 0x04008050); out_be32(&mmdc->mdscr, 0x00048033); out_be32(&mmdc->mppdcmpr2, 0x00000001); - out_be32(&mmdc->mprddlhwctl, 0x00000010); - - mdelay(400); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010); out_be32(&mmdc->mdscr, 0x00008033); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); - /* PD, SR */ out_be32(&mmdc->mdpdc, 0x00030035); out_be32(&mmdc->mapsr, 0x00001067); /* refresh scheme */ - out_be32(&mmdc->mdref, 0x103e8000); - - mdelay(400); + set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001); /* disable CON_REQ */ out_be32(&mmdc->mdscr, 0x0); +} - mdelay(50); +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; } int dram_init(void) @@ -183,6 +188,8 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 4a7aaaa..f7b9bce 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -23,6 +23,20 @@ DECLARE_GLOBAL_DATA_PTR; +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + int checkboard(void) { u8 in1; @@ -67,7 +81,7 @@ void mmdc_init(void) out_be32(&mmdc->mdscr, 0x00008000); /* configure timing parms */ - out_be32(&mmdc->mdotc, 0x12554000); + out_be32(&mmdc->mdotc, 0x12554000); out_be32(&mmdc->mdcfg0, 0xbabf7954); out_be32(&mmdc->mdcfg1, 0xff328f64); out_be32(&mmdc->mdcfg2, 0x01ff00db); @@ -79,7 +93,7 @@ void mmdc_init(void) out_be32(&mmdc->mpodtctrl, 0x0000022a); /* out of reset delays */ - out_be32(&mmdc->mdor, 0x00bf1023); + out_be32(&mmdc->mdor, 0x00bf1023); /* physical parms */ out_be32(&mmdc->mdctl, 0x05180000); @@ -96,69 +110,47 @@ void mmdc_init(void) /* dram init sequence: ZQCL */ out_be32(&mmdc->mdscr, 0x04008040); - out_be32(&mmdc->mpzqhwctrl, 0xa1390003); - - mdelay(100); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000); /* Calibrations now: wr lvl */ out_be32(&mmdc->mdscr, 0x00848031); out_be32(&mmdc->mdscr, 0x00008200); - out_be32(&mmdc->mpwlgcr, 0x00000001); + set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001); - mdelay(100); + mdelay(1); out_be32(&mmdc->mdscr, 0x00048031); out_be32(&mmdc->mdscr, 0x00008000); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); + mdelay(1); /* Calibrations now: Read DQS gating calibration */ out_be32(&mmdc->mdscr, 0x04008050); out_be32(&mmdc->mdscr, 0x00048033); out_be32(&mmdc->mppdcmpr2, 0x00000001); out_be32(&mmdc->mprddlctl, 0x40404040); - out_be32(&mmdc->mpdgctrl0, 0x10000000); - - mdelay(100); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000); out_be32(&mmdc->mdscr, 0x00008033); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); /* Calibrations now: Read calibration */ out_be32(&mmdc->mdscr, 0x04008050); out_be32(&mmdc->mdscr, 0x00048033); out_be32(&mmdc->mppdcmpr2, 0x00000001); - out_be32(&mmdc->mprddlhwctl, 0x00000010); - - mdelay(400); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010); out_be32(&mmdc->mdscr, 0x00008033); - /* manual_refresh */ - out_be32(&mmdc->mdscr, 0x00008020); - - mdelay(100); - /* PD, SR */ out_be32(&mmdc->mdpdc, 0x00030035); out_be32(&mmdc->mapsr, 0x00001067); /* refresh scheme */ - out_be32(&mmdc->mdref, 0x103e8000); - - mdelay(400); + set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001); /* disable CON_REQ */ out_be32(&mmdc->mdscr, 0x0); - - mdelay(50); } int dram_init(void) -- 1.7.9.5