From 080dc619d4780a1f7b14082b77b28686e694f72d Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 15 Dec 2020 13:56:46 +0100 Subject: toolchain: gcc: Remove support for GCC 5 GCC was used in 17.01 as the default compiler the last time. We do not test this old GCC version any more and there are some known problems it fails to compile the U-Boot for the Allwinner A64 SoC. Just remove it to make it clear that we will not support this old GCC version any more. Signed-off-by: Hauke Mehrtens Acked-by: Paul Spooren --- .../patches/5.5.0/040-fix-mips-ICE-PR-68400.patch | 23 ---------------------- 1 file changed, 23 deletions(-) delete mode 100644 toolchain/gcc/patches/5.5.0/040-fix-mips-ICE-PR-68400.patch (limited to 'toolchain/gcc/patches/5.5.0/040-fix-mips-ICE-PR-68400.patch') diff --git a/toolchain/gcc/patches/5.5.0/040-fix-mips-ICE-PR-68400.patch b/toolchain/gcc/patches/5.5.0/040-fix-mips-ICE-PR-68400.patch deleted file mode 100644 index e88af34032..0000000000 --- a/toolchain/gcc/patches/5.5.0/040-fix-mips-ICE-PR-68400.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/gcc/config/mips/mips.c -+++ b/gcc/config/mips/mips.c -@@ -8001,9 +8001,17 @@ mask_low_and_shift_p (machine_mode mode, - bool - and_operands_ok (machine_mode mode, rtx op1, rtx op2) - { -- return (memory_operand (op1, mode) -- ? and_load_operand (op2, mode) -- : and_reg_operand (op2, mode)); -+ if (!memory_operand (op1, mode)) -+ return and_reg_operand (op2, mode); -+ -+ if (!and_load_operand (op2, mode)) -+ return false; -+ -+ if (!TARGET_MIPS16 || si_mask_operand(op2, mode)) -+ return true; -+ -+ op1 = XEXP (op1, 0); -+ return !(REG_P (op1) && REGNO (op1) == STACK_POINTER_REGNUM); - } - - /* The canonical form of a mask-low-and-shift-left operation is -- cgit v1.2.3