From fb7bc0d4886a352d60a0f10ce5d6e3c4687799fe Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Sun, 26 Jul 2009 16:21:43 +0000 Subject: upgrade ppc40x to 2.6.30, unify magicbox and openrb board cuimages git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17018 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ppc40x/Makefile | 4 +- target/linux/ppc40x/config-2.6.30 | 8 +- target/linux/ppc40x/image/Makefile | 34 +- .../linux/ppc40x/patches-2.6.30/004-magicbox.patch | 427 +++++++++++++++++++++ .../ppc40x/patches-2.6.30/005-magicboxv1.patch | 314 --------------- .../linux/ppc40x/patches-2.6.30/005-openrb.patch | 404 +++++++++++++++++++ .../ppc40x/patches-2.6.30/006-magicboxv2.patch | 406 -------------------- .../ppc40x/patches-2.6.30/007-openrb-light.patch | 375 ------------------ .../ppc40x/patches-2.6.30/008-openrb-medium.patch | 404 ------------------- .../patches-2.6.30/100-magicbox-ide-driver.patch | 2 +- .../101-pata-magicbox-cf-driver.patch | 2 +- 11 files changed, 847 insertions(+), 1533 deletions(-) create mode 100644 target/linux/ppc40x/patches-2.6.30/004-magicbox.patch delete mode 100644 target/linux/ppc40x/patches-2.6.30/005-magicboxv1.patch create mode 100644 target/linux/ppc40x/patches-2.6.30/005-openrb.patch delete mode 100644 target/linux/ppc40x/patches-2.6.30/006-magicboxv2.patch delete mode 100644 target/linux/ppc40x/patches-2.6.30/007-openrb-light.patch delete mode 100644 target/linux/ppc40x/patches-2.6.30/008-openrb-medium.patch (limited to 'target') diff --git a/target/linux/ppc40x/Makefile b/target/linux/ppc40x/Makefile index b7e584ff01..d46dcbac6a 100644 --- a/target/linux/ppc40x/Makefile +++ b/target/linux/ppc40x/Makefile @@ -9,9 +9,9 @@ include $(TOPDIR)/rules.mk ARCH:=powerpc BOARD:=ppc40x BOARDNAME:=AMCC/IBM PPC40x -FEATURES:=squashfs jffs2 usb +FEATURES:=squashfs usb -LINUX_VERSION:=2.6.28.10 +LINUX_VERSION:=2.6.30.2 LINUX_KARCH:=powerpc include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/ppc40x/config-2.6.30 b/target/linux/ppc40x/config-2.6.30 index 9854f663fc..b650877fe3 100644 --- a/target/linux/ppc40x/config-2.6.30 +++ b/target/linux/ppc40x/config-2.6.30 @@ -27,7 +27,7 @@ CONFIG_BITREVERSE=y # CONFIG_BOOKE_WDT is not set CONFIG_BOUNCE=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd" +CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 noinitrd" CONFIG_CMDLINE_BOOL=y CONFIG_CONSISTENT_SIZE=0x00200000 # CONFIG_CPU_FREQ is not set @@ -111,8 +111,7 @@ CONFIG_KILAUEA=y # CONFIG_LEDS_GPIO is not set CONFIG_LOWMEM_SIZE=0x30000000 # CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_MAGICBOXV1=y -CONFIG_MAGICBOXV2=y +CONFIG_MAGICBOX=y # CONFIG_MAKALU is not set # CONFIG_MATH_EMULATION is not set # CONFIG_MMIO_NVRAM is not set @@ -129,8 +128,7 @@ CONFIG_NOT_COHERENT_CACHE=y CONFIG_OF=y CONFIG_OF_DEVICE=y CONFIG_OF_GPIO=y -CONFIG_OPENRB_LIGHT=y -CONFIG_OPENRB_MEDIUM=y +CONFIG_OPENRB=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_PCI=y diff --git a/target/linux/ppc40x/image/Makefile b/target/linux/ppc40x/image/Makefile index 3afeeca4ad..e03ffd93c8 100644 --- a/target/linux/ppc40x/image/Makefile +++ b/target/linux/ppc40x/image/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2008 OpenWrt.org +# Copyright (C) 2008-2009 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. @@ -36,21 +36,13 @@ endef define Image/Build/jffs2-64k ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicboxv1 bs=1152k conv=sync; \ + dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicbox bs=1152k conv=sync; \ dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-magicboxv1-jffs2.img + ) > $(BIN_DIR)/openwrt-$(BOARD)-magicbox-jffs2.img ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicboxv2 bs=1152k conv=sync; \ + dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb bs=1152k conv=sync; \ dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-magicboxv2-jffs2.img - ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb-light bs=1152k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-light-jffs2.img - ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb-medium bs=1152k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-medium-jffs2.img + ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-jffs2.img endef define Image/Build/squashfs @@ -61,21 +53,13 @@ define Image/Build/squashfs dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ ) > $(BIN_DIR)/openwrt-$(BOARD)-kilauea-$(1).img ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicboxv1 bs=1152k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-magicboxv1-$(1).img - ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicboxv2 bs=1152k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-magicboxv2-$(1).img - ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb-light bs=1152k conv=sync; \ + dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.magicbox bs=1152k conv=sync; \ dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-light-$(1).img + ) > $(BIN_DIR)/openwrt-$(BOARD)-magicbox-$(1).img ( \ - dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb-medium bs=1152k conv=sync; \ + dd if=$(LINUX_DIR)/arch/powerpc/boot/cuImage.openrb bs=1152k conv=sync; \ dd if=$(KDIR)/root.$(1) bs=64k conv=sync; \ - ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-medium-$(1).img + ) > $(BIN_DIR)/openwrt-$(BOARD)-openrb-$(1).img endef $(eval $(call BuildImage)) diff --git a/target/linux/ppc40x/patches-2.6.30/004-magicbox.patch b/target/linux/ppc40x/patches-2.6.30/004-magicbox.patch new file mode 100644 index 0000000000..a1a9da8b4c --- /dev/null +++ b/target/linux/ppc40x/patches-2.6.30/004-magicbox.patch @@ -0,0 +1,427 @@ +--- /dev/null ++++ b/arch/powerpc/boot/cuboot-magicbox.c +@@ -0,0 +1,90 @@ ++/* ++ * Old U-boot compatibility for Magicbox boards ++ * ++ * Author: Imre Kaloz ++ * Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ops.h" ++#include "io.h" ++#include "dcr.h" ++#include "stdio.h" ++#include "4xx.h" ++#include "44x.h" ++#include "cuboot.h" ++ ++#define TARGET_4xx ++#define TARGET_405EP ++#include "ppcboot.h" ++ ++static bd_t bd; ++ ++static void fixup_cf_card(void) ++{ ++#define DCRN_CPC0_PCI_BASE 0xf9 ++#define CF_CS0_BASE 0xff100000 ++#define CF_CS1_BASE 0xff200000 ++ ++ /* Turn on PerWE instead of PCIsomething */ ++ mtdcr(DCRN_CPC0_PCI_BASE, ++ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); ++ ++ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR); ++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP); ++ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); ++ ++ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR); ++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP); ++ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); ++ ++#undef DCRN_CPC0_PCI_BASE ++#undef CF_CS0_BASE ++#undef CF_CS1_BASE ++} ++ ++static void magicbox_fixups(void) ++{ ++ ibm405ep_fixup_clocks(bd.bi_procfreq / 8); ++ ibm4xx_sdram_fixup_memsize(); ++ ++ /* Magicbox v1 has only one ethernet, one serial and no ++ * CF slot -- detect it using it's fake enet1addr ++ */ ++ if ((bd.bi_enet1addr[0] == 0x00) && ++ (bd.bi_enet1addr[1] == 0x00) && ++ (bd.bi_enet1addr[2] == 0x02) && ++ (bd.bi_enet1addr[3] == 0xfa) && ++ (bd.bi_enet1addr[4] == 0xf0) && ++ (bd.bi_enet1addr[5] == 0x80)) { ++ void *devp; ++ ++ devp = finddevice("/plb/opb/ethernet@ef600900"); ++ del_node(devp); ++ devp = finddevice("/plb/opb/serial@ef600400"); ++ del_node(devp); ++ devp = finddevice("/plb/ebc/cf_card@ff100000"); ++ del_node(devp); ++ } else { ++ fixup_cf_card(); ++ } ++ ++ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); ++} ++ ++void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ++ unsigned long r6, unsigned long r7) ++{ ++ CUBOOT_INIT(); ++ platform_ops.fixups = magicbox_fixups; ++ platform_ops.exit = ibm40x_dbcr_reset; ++ fdt_init(_dtb_start); ++ serial_console_init(); ++} +--- /dev/null ++++ b/arch/powerpc/boot/dts/magicbox.dts +@@ -0,0 +1,281 @@ ++/* ++ * Device Tree Source for Magicbox boards ++ * ++ * Copyright 2008-2009 Imre Kaloz ++ * Copyright 2009 Gabor Juhos ++ * ++ * Based on walnut.dts ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "magicbox"; ++ compatible = "magicbox"; ++ dcr-parent = <&{/cpus/cpu@0}>; ++ ++ aliases { ++ ethernet0 = &EMAC0; ++ ethernet1 = &EMAC1; ++ serial0 = &UART0; ++ serial1 = &UART1; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ model = "PowerPC,405EP"; ++ reg = <0x00000000>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ timebase-frequency = <0>; /* Filled in by zImage */ ++ i-cache-line-size = <0x20>; ++ d-cache-line-size = <0x20>; ++ i-cache-size = <0x4000>; ++ d-cache-size = <0x4000>; ++ dcr-controller; ++ dcr-access-method = "native"; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ ++ }; ++ ++ UIC0: interrupt-controller { ++ compatible = "ibm,uic"; ++ interrupt-controller; ++ cell-index = <0>; ++ dcr-reg = <0x0c0 0x009>; ++ #address-cells = <0>; ++ #size-cells = <0>; ++ #interrupt-cells = <2>; ++ }; ++ ++ plb { ++ compatible = "ibm,plb3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ SDRAM0: memory-controller { ++ compatible = "ibm,sdram-405ep"; ++ dcr-reg = <0x010 0x002>; ++ }; ++ ++ MAL: mcmal { ++ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; ++ dcr-reg = <0x180 0x062>; ++ num-tx-chans = <4>; ++ num-rx-chans = <2>; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0xb 0x4 /* TXEOB */ ++ 0xc 0x4 /* RXEOB */ ++ 0xa 0x4 /* SERR */ ++ 0xd 0x4 /* TXDE */ ++ 0xe 0x4 /* RXDE */>; ++ }; ++ ++ POB0: opb { ++ compatible = "ibm,opb-405ep", "ibm,opb"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0xef600000 0xef600000 0x00a00000>; ++ dcr-reg = <0x0a0 0x005>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ UART0: serial@ef600300 { ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0xef600300 0x00000008>; ++ virtual-reg = <0xef600300>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ current-speed = <115200>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x0 0x4>; ++ }; ++ ++ UART1: serial@ef600400 { ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0xef600400 0x00000008>; ++ virtual-reg = <0xef600400>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ current-speed = <115200>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x1 0x4>; ++ }; ++ ++ IIC: i2c@ef600500 { ++ compatible = "ibm,iic-405ep", "ibm,iic"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0xef600500 0x00000011>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x2 0x4>; ++ ++ dtt@48 { ++ compatible = "national,lm75"; ++ reg = <0x48>; ++ }; ++ ++ eeprom@50 { ++ compatible = "at24,24c16"; ++ reg = <0x50>; ++ }; ++ }; ++ ++ GPIO0: gpio-controller@ef600700 { ++ compatible = "ibm,ppc4xx-gpio"; ++ reg = <0xef600700 0x00000020>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ }; ++ ++ EMAC0: ethernet@ef600800 { ++ linux,network-index = <0x0>; ++ device_type = "network"; ++ compatible = "ibm,emac-405ep", "ibm,emac"; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0xf 0x4 /* Ethernet */ ++ 0x9 0x4 /* Ethernet Wake Up */>; ++ local-mac-address = [000000000000]; /* Filled in by zImage */ ++ reg = <0xef600800 0x00000070>; ++ mal-device = <&MAL>; ++ mal-tx-channel = <0>; ++ mal-rx-channel = <0>; ++ cell-index = <0>; ++ max-frame-size = <0x5dc>; ++ rx-fifo-size = <0x1000>; ++ tx-fifo-size = <0x800>; ++ phy-mode = "mii"; ++ phy-map = <0x00000000>; ++ }; ++ ++ EMAC1: ethernet@ef600900 { ++ linux,network-index = <0x1>; ++ device_type = "network"; ++ compatible = "ibm,emac-405ep", "ibm,emac"; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0x11 0x4 /* Ethernet */ ++ 0x09 0x4 /* Ethernet Wake Up */>; ++ local-mac-address = [000000000000]; /* Filled in by zImage */ ++ reg = <0xef600900 0x00000070>; ++ mal-device = <&MAL>; ++ mal-tx-channel = <2>; ++ mal-rx-channel = <1>; ++ cell-index = <1>; ++ max-frame-size = <0x5dc>; ++ rx-fifo-size = <0x1000>; ++ tx-fifo-size = <0x800>; ++ mdio-device = <&EMAC0>; ++ phy-mode = "mii"; ++ phy-map = <0x00000001>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ user { ++ label = "magicbox:red:user"; ++ gpios = <&GPIO0 2 1>; ++ }; ++ }; ++ }; ++ ++ EBC0: ebc { ++ compatible = "ibm,ebc-405ep", "ibm,ebc"; ++ dcr-reg = <0x012 0x002>; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ /* The ranges property is supplied by the bootwrapper ++ * and is based on the firmware's configuration of the ++ * EBC bridge ++ */ ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ cf_card@ff100000 { ++ compatible = "magicbox-cf", "pata-magicbox-cf"; ++ reg = <0x00000000 0xff100000 0x00001000 ++ 0x00000000 0xff200000 0x00001000>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >; ++ }; ++ ++ nor_flash@ffc00000 { ++ compatible = "cfi-flash"; ++ bank-width = <2>; ++ reg = <0x00000000 0xffc00000 0x00400000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "linux"; ++ reg = <0x0 0x120000>; ++ }; ++ partition@120000 { ++ label = "rootfs"; ++ reg = <0x120000 0x2a0000>; ++ }; ++ partition@3c0000 { ++ label = "u-boot"; ++ reg = <0x3c0000 0x30000>; ++ read-only; ++ }; ++ }; ++ }; ++ ++ PCI0: pci@ec000000 { ++ device_type = "pci"; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ #address-cells = <3>; ++ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; ++ primary; ++ reg = <0xeec00000 0x00000008 /* Config space access */ ++ 0xeed80000 0x00000004 /* IACK */ ++ 0xeed80000 0x00000004 /* Special cycle */ ++ 0xef480000 0x00000040>; /* Internal registers */ ++ ++ /* Outbound ranges, one memory and one IO, ++ * later cannot be changed. Chip supports a second ++ * IO range but we don't use it for now ++ */ ++ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 ++ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; ++ ++ /* Inbound 2GB range starting at 0 */ ++ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; ++ ++ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; ++ interrupt-map = < ++ /* IDSEL 1 */ ++ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 ++ ++ /* IDSEL 2 */ ++ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 ++ ++ /* IDSEL 3 */ ++ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 ++ ++ /* IDSEL 4 */ ++ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 ++ >; ++ }; ++ }; ++ ++ chosen { ++ linux,stdout-path = "/plb/opb/serial@ef600300"; ++ }; ++}; +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -75,7 +75,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82 + cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ + cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ + virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ +- cuboot-acadia.c cuboot-amigaone.c ++ cuboot-acadia.c cuboot-amigaone.c cuboot-magicbox.c + src-boot := $(src-wlib) $(src-plat) empty.c + + src-boot := $(addprefix $(obj)/, $(src-boot)) +@@ -192,6 +192,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag + image-$(CONFIG_EP405) += dtbImage.ep405 + image-$(CONFIG_WALNUT) += treeImage.walnut + image-$(CONFIG_ACADIA) += cuImage.acadia ++image-$(CONFIG_MAGICBOX) += cuImage.magicbox + + # Board ports in arch/powerpc/platform/44x/Kconfig + image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony +--- a/arch/powerpc/platforms/40x/Kconfig ++++ b/arch/powerpc/platforms/40x/Kconfig +@@ -49,6 +49,16 @@ config KILAUEA + help + This option enables support for the AMCC PPC405EX evaluation board. + ++config MAGICBOX ++ bool "Magicbox" ++ depends on 40x ++ default n ++ select PPC40x_SIMPLE ++ select 405EP ++ select PCI ++ help ++ This option enables support for the Magicbox boards. ++ + config MAKALU + bool "Makalu" + depends on 40x +--- a/arch/powerpc/platforms/40x/ppc40x_simple.c ++++ b/arch/powerpc/platforms/40x/ppc40x_simple.c +@@ -51,7 +51,8 @@ machine_device_initcall(ppc40x_simple, p + * board.c file for it rather than adding it to this list. + */ + static char *board[] __initdata = { +- "amcc,acadia" ++ "amcc,acadia", ++ "magicbox" + }; + + static int __init ppc40x_probe(void) diff --git a/target/linux/ppc40x/patches-2.6.30/005-magicboxv1.patch b/target/linux/ppc40x/patches-2.6.30/005-magicboxv1.patch deleted file mode 100644 index 990eb53350..0000000000 --- a/target/linux/ppc40x/patches-2.6.30/005-magicboxv1.patch +++ /dev/null @@ -1,314 +0,0 @@ ---- /dev/null -+++ b/arch/powerpc/boot/cuboot-magicboxv1.c -@@ -0,0 +1,41 @@ -+/* -+ * Old U-boot compatibility for Magicbox v1 -+ * -+ * Author: Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ops.h" -+#include "io.h" -+#include "dcr.h" -+#include "stdio.h" -+#include "4xx.h" -+#include "44x.h" -+#include "cuboot.h" -+ -+#define TARGET_4xx -+#define TARGET_405EP -+#include "ppcboot.h" -+ -+static bd_t bd; -+ -+static void magicboxv1_fixups(void) -+{ -+ ibm405ep_fixup_clocks(25000000); -+ ibm4xx_sdram_fixup_memsize(); -+ dt_fixup_mac_addresses(&bd.bi_enetaddr); -+} -+ -+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, -+ unsigned long r6, unsigned long r7) -+{ -+ CUBOOT_INIT(); -+ platform_ops.fixups = magicboxv1_fixups; -+ platform_ops.exit = ibm40x_dbcr_reset; -+ fdt_init(_dtb_start); -+ serial_console_init(); -+} -+ ---- /dev/null -+++ b/arch/powerpc/boot/dts/magicboxv1.dts -@@ -0,0 +1,217 @@ -+/* -+ * Device Tree Source for Magicbox v1 -+ * -+ * Copyright 2008 Imre Kaloz -+ * -+ * Based on walnut.dts -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without -+ * any warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "magicboxv1"; -+ compatible = "magicboxv1"; -+ dcr-parent = <&{/cpus/cpu@0}>; -+ -+ aliases { -+ ethernet0 = &EMAC; -+ serial0 = &UART; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ model = "PowerPC,405EP"; -+ reg = <0x00000000>; -+ clock-frequency = <0xbebc200>; /* Filled in by zImage */ -+ timebase-frequency = <0>; /* Filled in by zImage */ -+ i-cache-line-size = <20>; -+ d-cache-line-size = <20>; -+ i-cache-size = <4000>; -+ d-cache-size = <4000>; -+ dcr-controller; -+ dcr-access-method = "native"; -+ }; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ -+ }; -+ -+ UIC0: interrupt-controller { -+ compatible = "ibm,uic"; -+ interrupt-controller; -+ cell-index = <0>; -+ dcr-reg = <0x0c0 0x009>; -+ #address-cells = <0>; -+ #size-cells = <0>; -+ #interrupt-cells = <2>; -+ }; -+ -+ plb { -+ compatible = "ibm,plb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ SDRAM0: memory-controller { -+ compatible = "ibm,sdram-405ep"; -+ dcr-reg = <0x010 0x002>; -+ }; -+ -+ MAL: mcmal { -+ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; -+ dcr-reg = <0x180 0x062>; -+ num-tx-chans = <4>; -+ num-rx-chans = <2>; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xb 0x4 /* TXEOB */ -+ 0xc 0x4 /* RXEOB */ -+ 0xa 0x4 /* SERR */ -+ 0xd 0x4 /* TXDE */ -+ 0xe 0x4 /* RXDE */>; -+ }; -+ -+ POB0: opb { -+ compatible = "ibm,opb-405ep", "ibm,opb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0xef600000 0xef600000 0x00a00000>; -+ dcr-reg = <0x0a0 0x005>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ UART: serial@ef600300 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600300 0x00000008>; -+ virtual-reg = <0xef600300>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x0 0x4>; -+ }; -+ -+ IIC: i2c@ef600500 { -+ compatible = "ibm,iic-405ep", "ibm,iic"; -+ reg = <0xef600500 0x00000011>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x2 0x4>; -+ }; -+ -+ GPIO: gpio@ef600700 { -+ compatible = "ibm,gpio-405ep"; -+ reg = <0xef600700 0x00000020>; -+ }; -+ -+ EMAC: ethernet@ef600800 { -+ linux,network-index = <0x0>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xf 0x4 /* Ethernet */ -+ 0x9 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600800 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <0>; -+ mal-rx-channel = <0>; -+ cell-index = <0>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ phy-mode = "mii"; -+ phy-map = <0x00000000>; -+ }; -+ -+ }; -+ -+ EBC0: ebc { -+ compatible = "ibm,ebc-405ep", "ibm,ebc"; -+ dcr-reg = <0x012 0x002>; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* The ranges property is supplied by the bootwrapper -+ * and is based on the firmware's configuration of the -+ * EBC bridge -+ */ -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ nor_flash@ffc00000 { -+ compatible = "cfi-flash"; -+ bank-width = <2>; -+ reg = <0x00000000 0xffc00000 0x00400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ partition@0 { -+ label = "linux"; -+ reg = <0x0 0x120000>; -+ }; -+ partition@120000 { -+ label = "rootfs"; -+ reg = <0x120000 0x2a0000>; -+ }; -+ partition@3c0000 { -+ label = "u-boot"; -+ reg = <0x3c0000 0x30000>; -+ read-only; -+ }; -+ }; -+ }; -+ -+ PCI0: pci@ec000000 { -+ device_type = "pci"; -+ #interrupt-cells = <1>; -+ #size-cells = <2>; -+ #address-cells = <3>; -+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; -+ primary; -+ reg = <0xeec00000 0x00000008 /* Config space access */ -+ 0xeed80000 0x00000004 /* IACK */ -+ 0xeed80000 0x00000004 /* Special cycle */ -+ 0xef480000 0x00000040>; /* Internal registers */ -+ -+ /* Outbound ranges, one memory and one IO, -+ * later cannot be changed. Chip supports a second -+ * IO range but we don't use it for now -+ */ -+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 -+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; -+ -+ /* Inbound 2GB range starting at 0 */ -+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; -+ -+ /* Magicbox v1 has all 4 IRQ pins tied together per slot */ -+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; -+ interrupt-map = < -+ /* IDSEL 1 */ -+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 -+ -+ /* IDSEL 2 */ -+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 -+ -+ /* IDSEL 3 */ -+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 -+ -+ /* IDSEL 4 */ -+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 -+ >; -+ }; -+ }; -+ -+ chosen { -+ linux,stdout-path = "/plb/opb/serial@ef600300"; -+ }; -+}; ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -75,7 +75,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82 - cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ - cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ -- cuboot-acadia.c cuboot-amigaone.c -+ cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c - src-boot := $(src-wlib) $(src-plat) empty.c - - src-boot := $(addprefix $(obj)/, $(src-boot)) -@@ -192,6 +192,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag - image-$(CONFIG_EP405) += dtbImage.ep405 - image-$(CONFIG_WALNUT) += treeImage.walnut - image-$(CONFIG_ACADIA) += cuImage.acadia -+image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1 - - # Board ports in arch/powerpc/platform/44x/Kconfig - image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony ---- a/arch/powerpc/platforms/40x/Kconfig -+++ b/arch/powerpc/platforms/40x/Kconfig -@@ -49,6 +49,16 @@ config KILAUEA - help - This option enables support for the AMCC PPC405EX evaluation board. - -+config MAGICBOXV1 -+ bool "Magicbox v1" -+ depends on 40x -+ default n -+ select PPC40x_SIMPLE -+ select 405EP -+ select PCI -+ help -+ This option enables support for the Magicbox v1 board. -+ - config MAKALU - bool "Makalu" - depends on 40x ---- a/arch/powerpc/platforms/40x/ppc40x_simple.c -+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c -@@ -51,7 +51,8 @@ machine_device_initcall(ppc40x_simple, p - * board.c file for it rather than adding it to this list. - */ - static char *board[] __initdata = { -- "amcc,acadia" -+ "amcc,acadia", -+ "magicboxv1", - }; - - static int __init ppc40x_probe(void) diff --git a/target/linux/ppc40x/patches-2.6.30/005-openrb.patch b/target/linux/ppc40x/patches-2.6.30/005-openrb.patch new file mode 100644 index 0000000000..0ad6740195 --- /dev/null +++ b/target/linux/ppc40x/patches-2.6.30/005-openrb.patch @@ -0,0 +1,404 @@ +--- /dev/null ++++ b/arch/powerpc/boot/cuboot-openrb.c +@@ -0,0 +1,71 @@ ++/* ++ * Old U-boot compatibility for OpenRB boards ++ * ++ * Author: Gabor Juhos ++ * Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ops.h" ++#include "io.h" ++#include "dcr.h" ++#include "stdio.h" ++#include "4xx.h" ++#include "44x.h" ++#include "cuboot.h" ++ ++#define TARGET_4xx ++#define TARGET_405EP ++#include "ppcboot.h" ++ ++static bd_t bd; ++ ++static void fixup_cf_card(void) ++{ ++#define DCRN_CPC0_PCI_BASE 0xf9 ++#define CF_CS0_BASE 0xff100000 ++#define CF_CS1_BASE 0xff200000 ++ ++ /* Turn on PerWE instead of PCIsomething */ ++ mtdcr(DCRN_CPC0_PCI_BASE, ++ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); ++ ++ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR); ++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP); ++ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); ++ ++ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR); ++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); ++ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP); ++ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); ++ ++#undef DCRN_CPC0_PCI_BASE ++#undef CF_CS0_BASE ++#undef CF_CS1_BASE ++} ++ ++static void openrb_fixups(void) ++{ ++ ibm405ep_fixup_clocks(bd.bi_procfreq / 8); ++ ibm4xx_sdram_fixup_memsize(); ++ ++ fixup_cf_card(); ++ ++ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); ++} ++ ++void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ++ unsigned long r6, unsigned long r7) ++{ ++ CUBOOT_INIT(); ++ platform_ops.fixups = openrb_fixups; ++ platform_ops.exit = ibm40x_dbcr_reset; ++ fdt_init(_dtb_start); ++ serial_console_init(); ++} +--- /dev/null ++++ b/arch/powerpc/boot/dts/openrb.dts +@@ -0,0 +1,276 @@ ++/* ++ * Device Tree Source for OpenRB boards ++ * ++ * Copyright 2009 Gabor Juhos ++ * Copyright 2009 Imre Kaloz ++ * ++ * Based on walnut.dts ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "openrb"; ++ compatible = "openrb"; ++ dcr-parent = <&{/cpus/cpu@0}>; ++ ++ aliases { ++ ethernet0 = &EMAC0; ++ ethernet1 = &EMAC1; ++ serial0 = &UART0; ++ serial1 = &UART1; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ model = "PowerPC,405EP"; ++ reg = <0x00000000>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ timebase-frequency = <0>; /* Filled in by zImage */ ++ i-cache-line-size = <0x20>; ++ d-cache-line-size = <0x20>; ++ i-cache-size = <0x4000>; ++ d-cache-size = <0x4000>; ++ dcr-controller; ++ dcr-access-method = "native"; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ ++ }; ++ ++ UIC0: interrupt-controller { ++ compatible = "ibm,uic"; ++ interrupt-controller; ++ cell-index = <0>; ++ dcr-reg = <0x0c0 0x009>; ++ #address-cells = <0>; ++ #size-cells = <0>; ++ #interrupt-cells = <2>; ++ }; ++ ++ plb { ++ compatible = "ibm,plb3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ SDRAM0: memory-controller { ++ compatible = "ibm,sdram-405ep"; ++ dcr-reg = <0x010 0x002>; ++ }; ++ ++ MAL: mcmal { ++ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; ++ dcr-reg = <0x180 0x062>; ++ num-tx-chans = <4>; ++ num-rx-chans = <2>; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0xb 0x4 /* TXEOB */ ++ 0xc 0x4 /* RXEOB */ ++ 0xa 0x4 /* SERR */ ++ 0xd 0x4 /* TXDE */ ++ 0xe 0x4 /* RXDE */>; ++ }; ++ ++ POB0: opb { ++ compatible = "ibm,opb-405ep", "ibm,opb"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0xef600000 0xef600000 0x00a00000>; ++ dcr-reg = <0x0a0 0x005>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ UART0: serial@ef600300 { ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0xef600300 0x00000008>; ++ virtual-reg = <0xef600300>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ current-speed = <115200>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x0 0x4>; ++ }; ++ ++ UART1: serial@ef600400 { ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <0xef600400 0x00000008>; ++ virtual-reg = <0xef600400>; ++ clock-frequency = <0>; /* Filled in by zImage */ ++ current-speed = <115200>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x1 0x4>; ++ }; ++ ++ IIC: i2c@ef600500 { ++ compatible = "ibm,iic-405ep", "ibm,iic"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0xef600500 0x00000011>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x2 0x4>; ++ ++ eeprom@50 { ++ compatible = "at24,24c16"; ++ reg = <0x50>; ++ }; ++ }; ++ ++ GPIO0: gpio-controller@ef600700 { ++ compatible = "ibm,ppc4xx-gpio"; ++ reg = <0xef600700 0x00000020>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ }; ++ ++ EMAC0: ethernet@ef600800 { ++ linux,network-index = <0x0>; ++ device_type = "network"; ++ compatible = "ibm,emac-405ep", "ibm,emac"; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0xf 0x4 /* Ethernet */ ++ 0x9 0x4 /* Ethernet Wake Up */>; ++ local-mac-address = [000000000000]; /* Filled in by zImage */ ++ reg = <0xef600800 0x00000070>; ++ mal-device = <&MAL>; ++ mal-tx-channel = <0>; ++ mal-rx-channel = <0>; ++ cell-index = <0>; ++ max-frame-size = <0x5dc>; ++ rx-fifo-size = <0x1000>; ++ tx-fifo-size = <0x800>; ++ phy-mode = "mii"; ++ phy-map = <0x00000000>; ++ }; ++ ++ EMAC1: ethernet@ef600900 { ++ linux,network-index = <0x1>; ++ device_type = "network"; ++ compatible = "ibm,emac-405ep", "ibm,emac"; ++ interrupt-parent = <&UIC0>; ++ interrupts = < ++ 0x11 0x4 /* Ethernet */ ++ 0x09 0x4 /* Ethernet Wake Up */>; ++ local-mac-address = [000000000000]; /* Filled in by zImage */ ++ reg = <0xef600900 0x00000070>; ++ mal-device = <&MAL>; ++ mal-tx-channel = <2>; ++ mal-rx-channel = <1>; ++ cell-index = <1>; ++ max-frame-size = <0x5dc>; ++ rx-fifo-size = <0x1000>; ++ tx-fifo-size = <0x800>; ++ mdio-device = <&EMAC0>; ++ phy-mode = "mii"; ++ phy-map = <0x00000001>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ user { ++ label = "openrb:green:user"; ++ gpios = <&GPIO0 2 1>; ++ }; ++ }; ++ }; ++ ++ EBC0: ebc { ++ compatible = "ibm,ebc-405ep", "ibm,ebc"; ++ dcr-reg = <0x012 0x002>; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ /* The ranges property is supplied by the bootwrapper ++ * and is based on the firmware's configuration of the ++ * EBC bridge ++ */ ++ clock-frequency = <0>; /* Filled in by zImage */ ++ ++ cf_card@ff100000 { ++ compatible = "magicbox-cf", "pata-magicbox-cf"; ++ reg = <0x00000000 0xff100000 0x00001000 ++ 0x00000000 0xff200000 0x00001000>; ++ interrupt-parent = <&UIC0>; ++ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >; ++ }; ++ ++ nor_flash@ff800000 { ++ compatible = "cfi-flash"; ++ bank-width = <2>; ++ reg = <0x00000000 0xff800000 0x00800000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "linux"; ++ reg = <0x0 0x120000>; ++ }; ++ partition@120000 { ++ label = "rootfs"; ++ reg = <0x120000 0x6a0000>; ++ }; ++ partition@7c0000 { ++ label = "u-boot"; ++ reg = <0x7c0000 0x30000>; ++ read-only; ++ }; ++ }; ++ }; ++ ++ PCI0: pci@ec000000 { ++ device_type = "pci"; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ #address-cells = <3>; ++ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; ++ primary; ++ reg = <0xeec00000 0x00000008 /* Config space access */ ++ 0xeed80000 0x00000004 /* IACK */ ++ 0xeed80000 0x00000004 /* Special cycle */ ++ 0xef480000 0x00000040>; /* Internal registers */ ++ ++ /* Outbound ranges, one memory and one IO, ++ * later cannot be changed. Chip supports a second ++ * IO range but we don't use it for now ++ */ ++ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 ++ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; ++ ++ /* Inbound 2GB range starting at 0 */ ++ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; ++ ++ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; ++ interrupt-map = < ++ /* IDSEL 1 */ ++ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 ++ ++ /* IDSEL 2 */ ++ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 ++ ++ /* IDSEL 3 */ ++ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 ++ ++ /* IDSEL 4 */ ++ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 ++ >; ++ }; ++ }; ++ ++ chosen { ++ linux,stdout-path = "/plb/opb/serial@ef600300"; ++ }; ++}; +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -75,7 +75,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82 + cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ + cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ + virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ +- cuboot-acadia.c cuboot-amigaone.c cuboot-magicbox.c ++ cuboot-acadia.c cuboot-amigaone.c cuboot-magicbox.c \ ++ cuboot-openrb.c + src-boot := $(src-wlib) $(src-plat) empty.c + + src-boot := $(addprefix $(obj)/, $(src-boot)) +@@ -193,6 +194,7 @@ image-$(CONFIG_EP405) += dtbImage.ep40 + image-$(CONFIG_WALNUT) += treeImage.walnut + image-$(CONFIG_ACADIA) += cuImage.acadia + image-$(CONFIG_MAGICBOX) += cuImage.magicbox ++image-$(CONFIG_OPENRB) += cuImage.openrb + + # Board ports in arch/powerpc/platform/44x/Kconfig + image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony +--- a/arch/powerpc/platforms/40x/Kconfig ++++ b/arch/powerpc/platforms/40x/Kconfig +@@ -59,6 +59,16 @@ config MAGICBOX + help + This option enables support for the Magicbox boards. + ++config OPENRB ++ bool "OpenRB" ++ depends on 40x ++ default n ++ select PPC40x_SIMPLE ++ select 405EP ++ select PCI ++ help ++ This option enables support for the OpenRB Light board. ++ + config MAKALU + bool "Makalu" + depends on 40x +--- a/arch/powerpc/platforms/40x/ppc40x_simple.c ++++ b/arch/powerpc/platforms/40x/ppc40x_simple.c +@@ -52,7 +52,8 @@ machine_device_initcall(ppc40x_simple, p + */ + static char *board[] __initdata = { + "amcc,acadia", +- "magicbox" ++ "magicbox", ++ "openrb" + }; + + static int __init ppc40x_probe(void) diff --git a/target/linux/ppc40x/patches-2.6.30/006-magicboxv2.patch b/target/linux/ppc40x/patches-2.6.30/006-magicboxv2.patch deleted file mode 100644 index 1fddad50c3..0000000000 --- a/target/linux/ppc40x/patches-2.6.30/006-magicboxv2.patch +++ /dev/null @@ -1,406 +0,0 @@ ---- /dev/null -+++ b/arch/powerpc/boot/cuboot-magicboxv2.c -@@ -0,0 +1,70 @@ -+/* -+ * Old U-boot compatibility for Magicbox v2 -+ * -+ * Author: Imre Kaloz -+ * Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ops.h" -+#include "io.h" -+#include "dcr.h" -+#include "stdio.h" -+#include "4xx.h" -+#include "44x.h" -+#include "cuboot.h" -+ -+#define TARGET_4xx -+#define TARGET_405EP -+#include "ppcboot.h" -+ -+static bd_t bd; -+ -+static void fixup_cf_card(void) -+{ -+#define DCRN_CPC0_PCI_BASE 0xf9 -+#define CF_CS0_BASE 0xff100000 -+#define CF_CS1_BASE 0xff200000 -+ -+ /* Turn on PerWE instead of PCIsomething */ -+ mtdcr(DCRN_CPC0_PCI_BASE, -+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); -+ -+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+#undef DCRN_CPC0_PCI_BASE -+#undef CF_CS0_BASE -+#undef CF_CS1_BASE -+} -+ -+static void magicboxv2_fixups(void) -+{ -+ fixup_cf_card(); -+ ibm405ep_fixup_clocks(25000000); -+ ibm4xx_sdram_fixup_memsize(); -+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); -+} -+ -+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, -+ unsigned long r6, unsigned long r7) -+{ -+ CUBOOT_INIT(); -+ platform_ops.fixups = magicboxv2_fixups; -+ platform_ops.exit = ibm40x_dbcr_reset; -+ fdt_init(_dtb_start); -+ serial_console_init(); -+} -+ ---- /dev/null -+++ b/arch/powerpc/boot/dts/magicboxv2.dts -@@ -0,0 +1,281 @@ -+/* -+ * Device Tree Source for Magicbox v2 -+ * -+ * Copyright 2008 Imre Kaloz -+ * Copyright 2009 Gabor Juhos -+ * -+ * Based on walnut.dts -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without -+ * any warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "magicboxv2"; -+ compatible = "magicboxv2"; -+ dcr-parent = <&{/cpus/cpu@0}>; -+ -+ aliases { -+ ethernet0 = &EMAC0; -+ ethernet1 = &EMAC1; -+ serial0 = &UART0; -+ serial1 = &UART1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ model = "PowerPC,405EP"; -+ reg = <0x00000000>; -+ clock-frequency = <0xbebc200>; /* Filled in by zImage */ -+ timebase-frequency = <0>; /* Filled in by zImage */ -+ i-cache-line-size = <20>; -+ d-cache-line-size = <20>; -+ i-cache-size = <4000>; -+ d-cache-size = <4000>; -+ dcr-controller; -+ dcr-access-method = "native"; -+ }; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ -+ }; -+ -+ UIC0: interrupt-controller { -+ compatible = "ibm,uic"; -+ interrupt-controller; -+ cell-index = <0>; -+ dcr-reg = <0x0c0 0x009>; -+ #address-cells = <0>; -+ #size-cells = <0>; -+ #interrupt-cells = <2>; -+ }; -+ -+ plb { -+ compatible = "ibm,plb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ SDRAM0: memory-controller { -+ compatible = "ibm,sdram-405ep"; -+ dcr-reg = <0x010 0x002>; -+ }; -+ -+ MAL: mcmal { -+ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; -+ dcr-reg = <0x180 0x062>; -+ num-tx-chans = <4>; -+ num-rx-chans = <2>; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xb 0x4 /* TXEOB */ -+ 0xc 0x4 /* RXEOB */ -+ 0xa 0x4 /* SERR */ -+ 0xd 0x4 /* TXDE */ -+ 0xe 0x4 /* RXDE */>; -+ }; -+ -+ POB0: opb { -+ compatible = "ibm,opb-405ep", "ibm,opb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0xef600000 0xef600000 0x00a00000>; -+ dcr-reg = <0x0a0 0x005>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ UART0: serial@ef600300 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600300 0x00000008>; -+ virtual-reg = <0xef600300>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x0 0x4>; -+ }; -+ -+ UART1: serial@ef600400 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600400 0x00000008>; -+ virtual-reg = <0xef600400>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x1 0x4>; -+ }; -+ -+ IIC: i2c@ef600500 { -+ compatible = "ibm,iic-405ep", "ibm,iic"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0xef600500 0x00000011>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x2 0x4>; -+ -+ dtt@48 { -+ compatible = "national,lm75"; -+ reg = <0x48>; -+ }; -+ -+ eeprom@50 { -+ compatible = "at24,24c16"; -+ reg = <0x50>; -+ }; -+ }; -+ -+ GPIO0: gpio-controller@ef600700 { -+ compatible = "ibm,ppc4xx-gpio"; -+ reg = <0xef600700 0x00000020>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ }; -+ -+ EMAC0: ethernet@ef600800 { -+ linux,network-index = <0x0>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xf 0x4 /* Ethernet */ -+ 0x9 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600800 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <0>; -+ mal-rx-channel = <0>; -+ cell-index = <0>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ phy-mode = "mii"; -+ phy-map = <0x00000000>; -+ }; -+ -+ EMAC1: ethernet@ef600900 { -+ linux,network-index = <0x1>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0x11 0x4 /* Ethernet */ -+ 0x09 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600900 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <2>; -+ mal-rx-channel = <1>; -+ cell-index = <1>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ mdio-device = <&EMAC0>; -+ phy-mode = "mii"; -+ phy-map = <0x00000001>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ user { -+ label = "magicbox:red:user"; -+ gpios = <&GPIO0 2 1>; -+ }; -+ }; -+ }; -+ -+ EBC0: ebc { -+ compatible = "ibm,ebc-405ep", "ibm,ebc"; -+ dcr-reg = <0x012 0x002>; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* The ranges property is supplied by the bootwrapper -+ * and is based on the firmware's configuration of the -+ * EBC bridge -+ */ -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ cf_card@ff100000 { -+ compatible = "magicbox-cf", "pata-magicbox-cf"; -+ reg = <0x00000000 0xff100000 0x00001000 -+ 0x00000000 0xff200000 0x00001000>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >; -+ }; -+ -+ nor_flash@ffc00000 { -+ compatible = "cfi-flash"; -+ bank-width = <2>; -+ reg = <0x00000000 0xffc00000 0x00400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ partition@0 { -+ label = "linux"; -+ reg = <0x0 0x120000>; -+ }; -+ partition@120000 { -+ label = "rootfs"; -+ reg = <0x120000 0x2a0000>; -+ }; -+ partition@3c0000 { -+ label = "u-boot"; -+ reg = <0x3c0000 0x30000>; -+ read-only; -+ }; -+ }; -+ }; -+ -+ PCI0: pci@ec000000 { -+ device_type = "pci"; -+ #interrupt-cells = <1>; -+ #size-cells = <2>; -+ #address-cells = <3>; -+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; -+ primary; -+ reg = <0xeec00000 0x00000008 /* Config space access */ -+ 0xeed80000 0x00000004 /* IACK */ -+ 0xeed80000 0x00000004 /* Special cycle */ -+ 0xef480000 0x00000040>; /* Internal registers */ -+ -+ /* Outbound ranges, one memory and one IO, -+ * later cannot be changed. Chip supports a second -+ * IO range but we don't use it for now -+ */ -+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 -+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; -+ -+ /* Inbound 2GB range starting at 0 */ -+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; -+ -+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; -+ interrupt-map = < -+ /* IDSEL 1 */ -+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 -+ -+ /* IDSEL 2 */ -+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 -+ -+ /* IDSEL 3 */ -+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 -+ -+ /* IDSEL 4 */ -+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 -+ >; -+ }; -+ }; -+ -+ chosen { -+ linux,stdout-path = "/plb/opb/serial@ef600300"; -+ }; -+}; ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -75,7 +75,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82 - cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ - cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ -- cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c -+ cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \ -+ cuboot-magicboxv2.c - src-boot := $(src-wlib) $(src-plat) empty.c - - src-boot := $(addprefix $(obj)/, $(src-boot)) -@@ -193,6 +194,7 @@ image-$(CONFIG_EP405) += dtbImage.ep40 - image-$(CONFIG_WALNUT) += treeImage.walnut - image-$(CONFIG_ACADIA) += cuImage.acadia - image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1 -+image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2 - - # Board ports in arch/powerpc/platform/44x/Kconfig - image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony ---- a/arch/powerpc/platforms/40x/Kconfig -+++ b/arch/powerpc/platforms/40x/Kconfig -@@ -59,6 +59,16 @@ config MAGICBOXV1 - help - This option enables support for the Magicbox v1 board. - -+config MAGICBOXV2 -+ bool "Magicbox v2" -+ depends on 40x -+ default n -+ select PPC40x_SIMPLE -+ select 405EP -+ select PCI -+ help -+ This option enables support for the Magicbox v2 board. -+ - config MAKALU - bool "Makalu" - depends on 40x ---- a/arch/powerpc/platforms/40x/ppc40x_simple.c -+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c -@@ -53,6 +53,7 @@ machine_device_initcall(ppc40x_simple, p - static char *board[] __initdata = { - "amcc,acadia", - "magicboxv1", -+ "magicboxv2", - }; - - static int __init ppc40x_probe(void) diff --git a/target/linux/ppc40x/patches-2.6.30/007-openrb-light.patch b/target/linux/ppc40x/patches-2.6.30/007-openrb-light.patch deleted file mode 100644 index 9048da5786..0000000000 --- a/target/linux/ppc40x/patches-2.6.30/007-openrb-light.patch +++ /dev/null @@ -1,375 +0,0 @@ ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82 - cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ - cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \ -- cuboot-magicboxv2.c -+ cuboot-magicboxv2.c cuboot-openrb-light.c - src-boot := $(src-wlib) $(src-plat) empty.c - - src-boot := $(addprefix $(obj)/, $(src-boot)) -@@ -195,6 +195,7 @@ image-$(CONFIG_WALNUT) += treeImage.wa - image-$(CONFIG_ACADIA) += cuImage.acadia - image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1 - image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2 -+image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light - - # Board ports in arch/powerpc/platform/44x/Kconfig - image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony ---- a/arch/powerpc/platforms/40x/Kconfig -+++ b/arch/powerpc/platforms/40x/Kconfig -@@ -79,6 +79,16 @@ config MAKALU - help - This option enables support for the AMCC PPC405EX board. - -+config OPENRB_LIGHT -+ bool "OpenRB Light" -+ depends on 40x -+ default n -+ select PPC40x_SIMPLE -+ select 405EP -+ select PCI -+ help -+ This option enables support for the OpenRB Light board. -+ - #config REDWOOD_5 - # bool "Redwood-5" - # depends on 40x ---- a/arch/powerpc/platforms/40x/ppc40x_simple.c -+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c -@@ -54,6 +54,7 @@ static char *board[] __initdata = { - "amcc,acadia", - "magicboxv1", - "magicboxv2", -+ "openrb,light", - }; - - static int __init ppc40x_probe(void) ---- /dev/null -+++ b/arch/powerpc/boot/cuboot-openrb-light.c -@@ -0,0 +1,69 @@ -+/* -+ * Old U-boot compatibility for OpenRB Light board -+ * -+ * Author: Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ops.h" -+#include "io.h" -+#include "dcr.h" -+#include "stdio.h" -+#include "4xx.h" -+#include "44x.h" -+#include "cuboot.h" -+ -+#define TARGET_4xx -+#define TARGET_405EP -+#include "ppcboot.h" -+ -+static bd_t bd; -+ -+static void fixup_cf_card(void) -+{ -+#define DCRN_CPC0_PCI_BASE 0xf9 -+#define CF_CS0_BASE 0xff100000 -+#define CF_CS1_BASE 0xff200000 -+ -+ /* Turn on PerWE instead of PCIsomething */ -+ mtdcr(DCRN_CPC0_PCI_BASE, -+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); -+ -+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+#undef DCRN_CPC0_PCI_BASE -+#undef CF_CS0_BASE -+#undef CF_CS1_BASE -+} -+ -+static void openrb_light_fixups(void) -+{ -+ fixup_cf_card(); -+ ibm405ep_fixup_clocks(33333000); -+ ibm4xx_sdram_fixup_memsize(); -+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); -+} -+ -+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, -+ unsigned long r6, unsigned long r7) -+{ -+ CUBOOT_INIT(); -+ platform_ops.fixups = openrb_light_fixups; -+ platform_ops.exit = ibm40x_dbcr_reset; -+ fdt_init(_dtb_start); -+ serial_console_init(); -+} -+ ---- /dev/null -+++ b/arch/powerpc/boot/dts/openrb-light.dts -@@ -0,0 +1,252 @@ -+/* -+ * Device Tree Source for OpenRB Light board -+ * -+ * Copyright 2009 Gabor Juhos -+ * -+ * Based on magicboxv2.dts -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without -+ * any warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "openrb,light"; -+ compatible = "openrb,light"; -+ dcr-parent = <&{/cpus/cpu@0}>; -+ -+ aliases { -+ ethernet0 = &EMAC0; -+ serial0 = &UART0; -+ serial1 = &UART1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ model = "PowerPC,405EP"; -+ reg = <0x00000000>; -+ clock-frequency = <0xbebc200>; /* Filled in by zImage */ -+ timebase-frequency = <0>; /* Filled in by zImage */ -+ i-cache-line-size = <20>; -+ d-cache-line-size = <20>; -+ i-cache-size = <4000>; -+ d-cache-size = <4000>; -+ dcr-controller; -+ dcr-access-method = "native"; -+ }; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ -+ }; -+ -+ UIC0: interrupt-controller { -+ compatible = "ibm,uic"; -+ interrupt-controller; -+ cell-index = <0>; -+ dcr-reg = <0x0c0 0x009>; -+ #address-cells = <0>; -+ #size-cells = <0>; -+ #interrupt-cells = <2>; -+ }; -+ -+ plb { -+ compatible = "ibm,plb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ SDRAM0: memory-controller { -+ compatible = "ibm,sdram-405ep"; -+ dcr-reg = <0x010 0x002>; -+ }; -+ -+ MAL: mcmal { -+ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; -+ dcr-reg = <0x180 0x062>; -+ num-tx-chans = <4>; -+ num-rx-chans = <2>; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xb 0x4 /* TXEOB */ -+ 0xc 0x4 /* RXEOB */ -+ 0xa 0x4 /* SERR */ -+ 0xd 0x4 /* TXDE */ -+ 0xe 0x4 /* RXDE */>; -+ }; -+ -+ OPB0: opb { -+ compatible = "ibm,opb-405ep", "ibm,opb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0xef600000 0xef600000 0x00a00000>; -+ dcr-reg = <0x0a0 0x005>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ UART0: serial@ef600300 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600300 0x00000008>; -+ virtual-reg = <0xef600300>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x0 0x4>; -+ }; -+ -+ UART1: serial@ef600400 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600400 0x00000008>; -+ virtual-reg = <0xef600400>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x1 0x4>; -+ }; -+ -+ IIC: i2c@ef600500 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "ibm,iic-405ep", "ibm,iic"; -+ reg = <0xef600500 0x00000011>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x2 0x4>; -+ -+ eeprom@50 { -+ compatible = "at24,24c16"; -+ reg = <0x50>; -+ }; -+ }; -+ -+ GPIO0: gpio-controller@ef600700 { -+ compatible = "ibm,ppc4xx-gpio"; -+ reg = <0xef600700 0x00000020>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ }; -+ -+ EMAC0: ethernet@ef600800 { -+ linux,network-index = <0x0>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xf 0x4 /* Ethernet */ -+ 0x9 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600800 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <0>; -+ mal-rx-channel = <0>; -+ cell-index = <0>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ phy-mode = "mii"; -+ phy-map = <0x00000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ user { -+ label = "openrb:green:user"; -+ gpios = <&GPIO0 2 1>; -+ }; -+ }; -+ }; -+ -+ EBC0: ebc { -+ compatible = "ibm,ebc-405ep", "ibm,ebc"; -+ dcr-reg = <0x012 0x002>; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* The ranges property is supplied by the bootwrapper -+ * and is based on the firmware's configuration of the -+ * EBC bridge -+ */ -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ cf_card@ff100000 { -+ compatible = "magicbox-cf", "pata-magicbox-cf"; -+ reg = <0x00000000 0xff100000 0x00001000 -+ 0x00000000 0xff200000 0x00001000>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >; -+ }; -+ -+ nor_flash@ff800000 { -+ compatible = "cfi-flash"; -+ bank-width = <2>; -+ reg = <0x00000000 0xff800000 0x00800000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ partition@0 { -+ label = "linux"; -+ reg = <0x0 0x120000>; -+ }; -+ partition@120000 { -+ label = "rootfs"; -+ reg = <0x120000 0x6a0000>; -+ }; -+ partition@7c0000 { -+ label = "u-boot"; -+ reg = <0x7c0000 0x30000>; -+ read-only; -+ }; -+ }; -+ }; -+ -+ PCI0: pci@ec000000 { -+ device_type = "pci"; -+ #interrupt-cells = <1>; -+ #size-cells = <2>; -+ #address-cells = <3>; -+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; -+ primary; -+ reg = <0xeec00000 0x00000008 /* Config space access */ -+ 0xeed80000 0x00000004 /* IACK */ -+ 0xeed80000 0x00000004 /* Special cycle */ -+ 0xef480000 0x00000040>; /* Internal registers */ -+ -+ /* Outbound ranges, one memory and one IO, -+ * later cannot be changed. Chip supports a second -+ * IO range but we don't use it for now -+ */ -+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 -+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; -+ -+ /* Inbound 2GB range starting at 0 */ -+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; -+ -+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; -+ interrupt-map = < -+ /* IDSEL 1 */ -+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 -+ -+ /* IDSEL 2 */ -+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 -+ -+ /* IDSEL 3 */ -+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 -+ -+ /* IDSEL 4 */ -+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 -+ >; -+ }; -+ }; -+ -+ chosen { -+ linux,stdout-path = "/plb/opb/serial@ef600300"; -+ }; -+}; diff --git a/target/linux/ppc40x/patches-2.6.30/008-openrb-medium.patch b/target/linux/ppc40x/patches-2.6.30/008-openrb-medium.patch deleted file mode 100644 index c7b7af0c3b..0000000000 --- a/target/linux/ppc40x/patches-2.6.30/008-openrb-medium.patch +++ /dev/null @@ -1,404 +0,0 @@ ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82 - cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ - cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \ -- cuboot-magicboxv2.c cuboot-openrb-light.c -+ cuboot-magicboxv2.c cuboot-openrb-light.c cuboot-openrb-medium.c - src-boot := $(src-wlib) $(src-plat) empty.c - - src-boot := $(addprefix $(obj)/, $(src-boot)) -@@ -196,6 +196,7 @@ image-$(CONFIG_ACADIA) += cuImage.acad - image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1 - image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2 - image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light -+image-$(CONFIG_OPENRB_MEDIUM) += cuImage.openrb-medium - - # Board ports in arch/powerpc/platform/44x/Kconfig - image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony ---- a/arch/powerpc/platforms/40x/Kconfig -+++ b/arch/powerpc/platforms/40x/Kconfig -@@ -89,6 +89,16 @@ config OPENRB_LIGHT - help - This option enables support for the OpenRB Light board. - -+config OPENRB_MEDIUM -+ bool "OpenRB Medium" -+ depends on 40x -+ default n -+ select PPC40x_SIMPLE -+ select 405EP -+ select PCI -+ help -+ This option enables support for the OpenRB Medium board. -+ - #config REDWOOD_5 - # bool "Redwood-5" - # depends on 40x ---- a/arch/powerpc/platforms/40x/ppc40x_simple.c -+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c -@@ -55,6 +55,7 @@ static char *board[] __initdata = { - "magicboxv1", - "magicboxv2", - "openrb,light", -+ "openrb,medium", - }; - - static int __init ppc40x_probe(void) ---- /dev/null -+++ b/arch/powerpc/boot/cuboot-openrb-medium.c -@@ -0,0 +1,69 @@ -+/* -+ * Old U-boot compatibility for OpenRB Medium -+ * -+ * Author: Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ops.h" -+#include "io.h" -+#include "dcr.h" -+#include "stdio.h" -+#include "4xx.h" -+#include "44x.h" -+#include "cuboot.h" -+ -+#define TARGET_4xx -+#define TARGET_405EP -+#include "ppcboot.h" -+ -+static bd_t bd; -+ -+static void fixup_cf_card(void) -+{ -+#define DCRN_CPC0_PCI_BASE 0xf9 -+#define CF_CS0_BASE 0xff100000 -+#define CF_CS1_BASE 0xff200000 -+ -+ /* Turn on PerWE instead of PCIsomething */ -+ mtdcr(DCRN_CPC0_PCI_BASE, -+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27)); -+ -+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */ -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR); -+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16); -+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP); -+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800); -+ -+#undef DCRN_CPC0_PCI_BASE -+#undef CF_CS0_BASE -+#undef CF_CS1_BASE -+} -+ -+static void openrb_light_fixups(void) -+{ -+ fixup_cf_card(); -+ ibm405ep_fixup_clocks(33333000); -+ ibm4xx_sdram_fixup_memsize(); -+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); -+} -+ -+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, -+ unsigned long r6, unsigned long r7) -+{ -+ CUBOOT_INIT(); -+ platform_ops.fixups = openrb_light_fixups; -+ platform_ops.exit = ibm40x_dbcr_reset; -+ fdt_init(_dtb_start); -+ serial_console_init(); -+} -+ ---- /dev/null -+++ b/arch/powerpc/boot/dts/openrb-medium.dts -@@ -0,0 +1,281 @@ -+/* -+ * Device Tree Source for OpenRB Medium board -+ * -+ * Copyright 2008 Imre Kaloz -+ * Copyright 2009 Gabor Juhos -+ * -+ * Based on walnut.dts -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without -+ * any warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ model = "openrb,medium"; -+ compatible = "openrb,medium"; -+ dcr-parent = <&{/cpus/cpu@0}>; -+ -+ aliases { -+ ethernet0 = &EMAC0; -+ ethernet1 = &EMAC1; -+ serial0 = &UART0; -+ serial1 = &UART1; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ model = "PowerPC,405EP"; -+ reg = <0x00000000>; -+ clock-frequency = <0xbebc200>; /* Filled in by zImage */ -+ timebase-frequency = <0>; /* Filled in by zImage */ -+ i-cache-line-size = <20>; -+ d-cache-line-size = <20>; -+ i-cache-size = <4000>; -+ d-cache-size = <4000>; -+ dcr-controller; -+ dcr-access-method = "native"; -+ }; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */ -+ }; -+ -+ UIC0: interrupt-controller { -+ compatible = "ibm,uic"; -+ interrupt-controller; -+ cell-index = <0>; -+ dcr-reg = <0x0c0 0x009>; -+ #address-cells = <0>; -+ #size-cells = <0>; -+ #interrupt-cells = <2>; -+ }; -+ -+ plb { -+ compatible = "ibm,plb3"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ SDRAM0: memory-controller { -+ compatible = "ibm,sdram-405ep"; -+ dcr-reg = <0x010 0x002>; -+ }; -+ -+ MAL: mcmal { -+ compatible = "ibm,mcmal-405ep", "ibm,mcmal"; -+ dcr-reg = <0x180 0x062>; -+ num-tx-chans = <4>; -+ num-rx-chans = <2>; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xb 0x4 /* TXEOB */ -+ 0xc 0x4 /* RXEOB */ -+ 0xa 0x4 /* SERR */ -+ 0xd 0x4 /* TXDE */ -+ 0xe 0x4 /* RXDE */>; -+ }; -+ -+ POB0: opb { -+ compatible = "ibm,opb-405ep", "ibm,opb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0xef600000 0xef600000 0x00a00000>; -+ dcr-reg = <0x0a0 0x005>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ UART0: serial@ef600300 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600300 0x00000008>; -+ virtual-reg = <0xef600300>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x0 0x4>; -+ }; -+ -+ UART1: serial@ef600400 { -+ device_type = "serial"; -+ compatible = "ns16550"; -+ reg = <0xef600400 0x00000008>; -+ virtual-reg = <0xef600400>; -+ clock-frequency = <0>; /* Filled in by zImage */ -+ current-speed = <115200>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x1 0x4>; -+ }; -+ -+ IIC: i2c@ef600500 { -+ compatible = "ibm,iic-405ep", "ibm,iic"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0xef600500 0x00000011>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x2 0x4>; -+ -+ dtt@48 { -+ compatible = "national,lm75"; -+ reg = <0x48>; -+ }; -+ -+ eeprom@50 { -+ compatible = "at24,24c16"; -+ reg = <0x50>; -+ }; -+ }; -+ -+ GPIO0: gpio-controller@ef600700 { -+ compatible = "ibm,ppc4xx-gpio"; -+ reg = <0xef600700 0x00000020>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ }; -+ -+ EMAC0: ethernet@ef600800 { -+ linux,network-index = <0x0>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0xf 0x4 /* Ethernet */ -+ 0x9 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600800 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <0>; -+ mal-rx-channel = <0>; -+ cell-index = <0>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ phy-mode = "mii"; -+ phy-map = <0x00000000>; -+ }; -+ -+ EMAC1: ethernet@ef600900 { -+ linux,network-index = <0x1>; -+ device_type = "network"; -+ compatible = "ibm,emac-405ep", "ibm,emac"; -+ interrupt-parent = <&UIC0>; -+ interrupts = < -+ 0x11 0x4 /* Ethernet */ -+ 0x09 0x4 /* Ethernet Wake Up */>; -+ local-mac-address = [000000000000]; /* Filled in by zImage */ -+ reg = <0xef600900 0x00000070>; -+ mal-device = <&MAL>; -+ mal-tx-channel = <2>; -+ mal-rx-channel = <1>; -+ cell-index = <1>; -+ max-frame-size = <0x5dc>; -+ rx-fifo-size = <0x1000>; -+ tx-fifo-size = <0x800>; -+ mdio-device = <&EMAC0>; -+ phy-mode = "mii"; -+ phy-map = <0x00000001>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ user { -+ label = "magicbox:red:user"; -+ gpios = <&GPIO0 2 1>; -+ }; -+ }; -+ }; -+ -+ EBC0: ebc { -+ compatible = "ibm,ebc-405ep", "ibm,ebc"; -+ dcr-reg = <0x012 0x002>; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* The ranges property is supplied by the bootwrapper -+ * and is based on the firmware's configuration of the -+ * EBC bridge -+ */ -+ clock-frequency = <0>; /* Filled in by zImage */ -+ -+ cf_card@ff100000 { -+ compatible = "magicbox-cf", "pata-magicbox-cf"; -+ reg = <0x00000000 0xff100000 0x00001000 -+ 0x00000000 0xff200000 0x00001000>; -+ interrupt-parent = <&UIC0>; -+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >; -+ }; -+ -+ nor_flash@ffc00000 { -+ compatible = "cfi-flash"; -+ bank-width = <2>; -+ reg = <0x00000000 0xffc00000 0x00400000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ partition@0 { -+ label = "linux"; -+ reg = <0x0 0x120000>; -+ }; -+ partition@120000 { -+ label = "rootfs"; -+ reg = <0x120000 0x2a0000>; -+ }; -+ partition@3c0000 { -+ label = "u-boot"; -+ reg = <0x3c0000 0x30000>; -+ read-only; -+ }; -+ }; -+ }; -+ -+ PCI0: pci@ec000000 { -+ device_type = "pci"; -+ #interrupt-cells = <1>; -+ #size-cells = <2>; -+ #address-cells = <3>; -+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci"; -+ primary; -+ reg = <0xeec00000 0x00000008 /* Config space access */ -+ 0xeed80000 0x00000004 /* IACK */ -+ 0xeed80000 0x00000004 /* Special cycle */ -+ 0xef480000 0x00000040>; /* Internal registers */ -+ -+ /* Outbound ranges, one memory and one IO, -+ * later cannot be changed. Chip supports a second -+ * IO range but we don't use it for now -+ */ -+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 -+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; -+ -+ /* Inbound 2GB range starting at 0 */ -+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; -+ -+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; -+ interrupt-map = < -+ /* IDSEL 1 */ -+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 -+ -+ /* IDSEL 2 */ -+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 -+ -+ /* IDSEL 3 */ -+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 -+ -+ /* IDSEL 4 */ -+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 -+ >; -+ }; -+ }; -+ -+ chosen { -+ linux,stdout-path = "/plb/opb/serial@ef600300"; -+ }; -+}; diff --git a/target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch b/target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch index ebd9b339e9..d6907f9828 100644 --- a/target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch +++ b/target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch @@ -6,7 +6,7 @@ +config BLK_DEV_IDE_MAGICBOX + tristate "Magicbox CF card support" -+ depends on MAGICBOXV2 || OPENRB_LIGHT ++ depends on MAGICBOX || OPENRB_LIGHT + select IDE_XFER_MODE + config BLK_DEV_IDE_TX4938 diff --git a/target/linux/ppc40x/patches-2.6.30/101-pata-magicbox-cf-driver.patch b/target/linux/ppc40x/patches-2.6.30/101-pata-magicbox-cf-driver.patch index 84794d9640..f738f89685 100644 --- a/target/linux/ppc40x/patches-2.6.30/101-pata-magicbox-cf-driver.patch +++ b/target/linux/ppc40x/patches-2.6.30/101-pata-magicbox-cf-driver.patch @@ -6,7 +6,7 @@ +config PATA_MAGICBOX_CF + tristate "Magicbox/OpenRB Compact Flash support" -+ depends on MAGICBOXV2 || OPENRB_LIGHT ++ depends on MAGICBOX || OPENRB + help + This option enables support for a Compact Flash conected on + the ppc405ep expansion bus. This driver had been written for -- cgit v1.2.3