From 4611fdd759d274cc6081f57d832413c9b40935b3 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 18 Oct 2022 22:19:34 +0200 Subject: ipq806x: 5.15: add 6.1 tag to upstream patch Add 6.1 tag to upstream patch now that 6.1 got tagged. This permits to track patch in a better way and directly drop them on kernel bump. Signed-off-by: Christian Marangi --- ...-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch | 129 ------------ ...-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch | 67 ------- ...-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch | 67 ------- ...-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch | 129 ++++++++++++ ...-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch | 67 +++++++ ...-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch | 67 +++++++ ...dings-clock-add-pcm-reset-for-ipq806x-lcc.patch | 29 --- ...clk-qcom-lcc-ipq806x-add-reset-definition.patch | 48 ----- ...k-qcom-lcc-ipq806x-convert-to-parent-data.patch | 217 --------------------- ...dings-clock-add-pcm-reset-for-ipq806x-lcc.patch | 29 +++ ...clk-qcom-lcc-ipq806x-add-reset-definition.patch | 48 +++++ ...k-qcom-lcc-ipq806x-convert-to-parent-data.patch | 217 +++++++++++++++++++++ ...ce-devm_-hw_register_mux_parent_data_tabl.patch | 46 ----- ...-qcom-kpss-xcc-convert-to-parent-data-API.patch | 70 ------- ...ce-devm_-hw_register_mux_parent_data_tabl.patch | 46 +++++ ...-qcom-kpss-xcc-convert-to-parent-data-API.patch | 70 +++++++ 16 files changed, 673 insertions(+), 673 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch delete mode 100644 target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch delete mode 100644 target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch delete mode 100644 target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch delete mode 100644 target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch delete mode 100644 target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch delete mode 100644 target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch delete mode 100644 target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch create mode 100644 target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch create mode 100644 target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch (limited to 'target/linux') diff --git a/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch b/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch deleted file mode 100644 index 8b20a550f6..0000000000 --- a/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:05:16 +0200 -Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant - -Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for -some additional pcie, sata and usb configuration values, additional -reserved memory and serial output. - -Signed-off-by: Christian Marangi ---- - .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++ - arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++ - 2 files changed, 106 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; -+ -+ aliases { -+ serial0 = &gsbi4_serial; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ rsvd@41200000 { -+ reg = <0x41200000 0x300000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&gsbi4 { -+ qcom,mode = ; -+ status = "okay"; -+ -+ serial@16340000 { -+ status = "okay"; -+ }; -+ /* -+ * The i2c device on gsbi4 should not be enabled. -+ * On ipq806x designs gsbi4 i2c is meant for exclusive -+ * RPM usage. Turning this on in kernel manifests as -+ * i2c failure for the RPM. -+ */ -+}; -+ -+&pcie0 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie1 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie2 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&sata { -+ ports-implemented = <0x1>; -+}; -+ -+&ss_phy_0 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; -+ -+&ss_phy_1 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch b/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch deleted file mode 100644 index fdff292480..0000000000 --- a/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:07:26 +0200 -Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant - -ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of -usb port and a reduced voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8062.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8062"; -+ compatible = "qcom,ipq8062", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch b/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch deleted file mode 100644 index bccc577b91..0000000000 --- a/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:09:35 +0200 -Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant - -ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and -an increased voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8065.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8065"; -+ compatible = "qcom,ipq8065", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch new file mode 100644 index 0000000000..8b20a550f6 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch @@ -0,0 +1,129 @@ +From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:05:16 +0200 +Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant + +Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for +some additional pcie, sata and usb configuration values, additional +reserved memory and serial output. + +Signed-off-by: Christian Marangi +--- + .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++ + arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++ + 2 files changed, 106 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +@@ -0,0 +1,69 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; ++ ++ aliases { ++ serial0 = &gsbi4_serial; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++}; ++ ++&gsbi4 { ++ qcom,mode = ; ++ status = "okay"; ++ ++ serial@16340000 { ++ status = "okay"; ++ }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ ++}; ++ ++&pcie0 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&pcie1 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&pcie2 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&sata { ++ ports-implemented = <0x1>; ++}; ++ ++&ss_phy_0 { ++ qcom,rx-eq = <2>; ++ qcom,tx-deamp_3_5db = <32>; ++ qcom,mpll = <5>; ++}; ++ ++&ss_phy_1 { ++ qcom,rx-eq = <2>; ++ qcom,tx-deamp_3_5db = <32>; ++ qcom,mpll = <5>; ++}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch new file mode 100644 index 0000000000..fdff292480 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch @@ -0,0 +1,67 @@ +From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:07:26 +0200 +Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant + +ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of +usb port and a reduced voltage output with the smb208 regulators. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include "qcom-ipq8062.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8062"; ++ compatible = "qcom,ipq8062", "qcom,ipq8064"; ++}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch new file mode 100644 index 0000000000..bccc577b91 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch @@ -0,0 +1,67 @@ +From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:09:35 +0200 +Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant + +ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and +an increased voltage output with the smb208 regulators. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8065.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = <775000>; ++ regulator-max-microvolt = <1275000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = <775000>; ++ regulator-max-microvolt = <1275000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8065"; ++ compatible = "qcom,ipq8065", "qcom,ipq8064"; ++}; diff --git a/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch deleted file mode 100644 index 72e70b613c..0000000000 --- a/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch +++ /dev/null @@ -1,29 +0,0 @@ -From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:13:32 +0200 -Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc - -Add pcm reset define for ipq806x lcc. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov -Acked-by: Rob Herring ---- -v3: - - Added review tag - - Added ack tag -v2: - - Fix Sob tag - - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,6 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 -+ - #endif diff --git a/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch deleted file mode 100644 index 2393651306..0000000000 --- a/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:19:55 +0200 -Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition - -Add reset definition for lcc-ipq806x. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov ---- -v3: - - Added review tag -v2: - - Fix Sob tag - - drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -22,6 +22,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl - [AHBIX_CLK] = &ahbix_clk.clkr, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct regmap_config lcc_ipq806x_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch deleted file mode 100644 index 905dc5bf40..0000000000 --- a/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch +++ /dev/null @@ -1,217 +0,0 @@ -From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:35:13 +0200 -Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data - -Convert lcc-ipq806x driver to parent_data API. - -Signed-off-by: Christian Marangi ---- -v5: -- Fix the same compilation error (don't know what the hell happen - to my buildroot) -v4: -- Fix compilation error -v3: - - Inline pxo pll4 parent - - Change .name from pxo to pxo_board - - drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- - 1 file changed, 42 insertions(+), 35 deletions(-) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll4", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "pxo", .name = "pxo_board", -+ }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p - { P_PLL4, 2 } - }; - --static const char * const lcc_pxo_pll4[] = { -- "pxo", -- "pll4_vote", -+static const struct clk_parent_data lcc_pxo_pll4[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .fw_name = "pll4_vote", .name = "pll4_vote" }, - }; - - static struct freq_tbl clk_tbl_aif_mi2s[] = { -@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_mi2s_parents[] = { -- "mi2s_osr_src", --}; -- - static struct clk_branch mi2s_osr_clk = { - .halt_reg = 0x50, - .halt_bit = 1, -@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_div_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, -@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_div_clk", -- .parent_names = (const char *[]){ "mi2s_div_clk" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_div_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl - }, - }; - -+static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { -+ { .hw = &mi2s_bit_div_clk.clkr.hw, }, -+ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, -+}; - - static struct clk_regmap_mux mi2s_bit_clk = { - .reg = 0x48, -@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_clk", -- .parent_names = (const char *[]){ -- "mi2s_bit_div_clk", -- "mi2s_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_mi2s_bit_div_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcm_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk_out", -- .parent_names = (const char *[]){ "pcm_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcm_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { - }, - }; - -+static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { -+ { .hw = &pcm_clk_out.clkr.hw, }, -+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, -+}; -+ - static struct clk_regmap_mux pcm_clk = { - .reg = 0x54, - .shift = 10, -@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk", -- .parent_names = (const char *[]){ -- "pcm_clk_out", -- "pcm_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_pcm_clk_out_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "spdif_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_spdif_parents[] = { -- "spdif_src", --}; -- - static struct clk_branch spdif_clk = { - .halt_reg = 0xd4, - .halt_bit = 1, -@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "spdif_clk", -- .parent_names = lcc_spdif_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &spdif_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "ahbix", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_lcc_ops, - }, - }, diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch new file mode 100644 index 0000000000..72e70b613c --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch @@ -0,0 +1,29 @@ +From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:13:32 +0200 +Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc + +Add pcm reset define for ipq806x lcc. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +Acked-by: Rob Herring +--- +v3: + - Added review tag + - Added ack tag +v2: + - Fix Sob tag + + include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h +@@ -19,4 +19,6 @@ + #define SPDIF_CLK 10 + #define AHBIX_CLK 11 + ++#define LCC_PCM_RESET 0 ++ + #endif diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch new file mode 100644 index 0000000000..2393651306 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch @@ -0,0 +1,48 @@ +From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:19:55 +0200 +Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition + +Add reset definition for lcc-ipq806x. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +--- +v3: + - Added review tag +v2: + - Fix Sob tag + + drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -22,6 +22,7 @@ + #include "clk-branch.h" + #include "clk-regmap-divider.h" + #include "clk-regmap-mux.h" ++#include "reset.h" + + static struct clk_pll pll4 = { + .l_reg = 0x4, +@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl + [AHBIX_CLK] = &ahbix_clk.clkr, + }; + ++static const struct qcom_reset_map lcc_ipq806x_resets[] = { ++ [LCC_PCM_RESET] = { 0x54, 13 }, ++}; ++ + static const struct regmap_config lcc_ipq806x_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq + .config = &lcc_ipq806x_regmap_config, + .clks = lcc_ipq806x_clks, + .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), ++ .resets = lcc_ipq806x_resets, ++ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), + }; + + static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch new file mode 100644 index 0000000000..905dc5bf40 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch @@ -0,0 +1,217 @@ +From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:35:13 +0200 +Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data + +Convert lcc-ipq806x driver to parent_data API. + +Signed-off-by: Christian Marangi +--- +v5: +- Fix the same compilation error (don't know what the hell happen + to my buildroot) +v4: +- Fix compilation error +v3: + - Inline pxo pll4 parent + - Change .name from pxo to pxo_board + + drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- + 1 file changed, 42 insertions(+), 35 deletions(-) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll4", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "pxo", .name = "pxo_board", ++ }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p + { P_PLL4, 2 } + }; + +-static const char * const lcc_pxo_pll4[] = { +- "pxo", +- "pll4_vote", ++static const struct clk_parent_data lcc_pxo_pll4[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .fw_name = "pll4_vote", .name = "pll4_vote" }, + }; + + static struct freq_tbl clk_tbl_aif_mi2s[] = { +@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_mi2s_parents[] = { +- "mi2s_osr_src", +-}; +- + static struct clk_branch mi2s_osr_clk = { + .halt_reg = 0x50, + .halt_bit = 1, +@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_div_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_div_clk", +- .parent_names = (const char *[]){ "mi2s_div_clk" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_div_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl + }, + }; + ++static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { ++ { .hw = &mi2s_bit_div_clk.clkr.hw, }, ++ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, ++}; + + static struct clk_regmap_mux mi2s_bit_clk = { + .reg = 0x48, +@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_clk", +- .parent_names = (const char *[]){ +- "mi2s_bit_div_clk", +- "mi2s_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_mi2s_bit_div_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcm_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk_out", +- .parent_names = (const char *[]){ "pcm_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcm_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { + }, + }; + ++static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { ++ { .hw = &pcm_clk_out.clkr.hw, }, ++ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, ++}; ++ + static struct clk_regmap_mux pcm_clk = { + .reg = 0x54, + .shift = 10, +@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk", +- .parent_names = (const char *[]){ +- "pcm_clk_out", +- "pcm_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_pcm_clk_out_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "spdif_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_spdif_parents[] = { +- "spdif_src", +-}; +- + static struct clk_branch spdif_clk = { + .halt_reg = 0xd4, + .halt_bit = 1, +@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "spdif_clk", +- .parent_names = lcc_spdif_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &spdif_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "ahbix", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_lcc_ops, + }, + }, diff --git a/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch b/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch deleted file mode 100644 index a15a723029..0000000000 --- a/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 12 Apr 2022 16:48:39 +0200 -Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table - API - -Introduce (devm_)hw_register_mux_parent_data_table new API. We have -basic support for clk_register_mux using parent_data but we lack any API -to provide a custom parent_map. Add these 2 new API to correctly handle -these special configuration instead of using the generic -__(devm_)clk_hw_register_mux API. - -Signed-off-by: Christian Marangi ---- - include/linux/clk-provider.h | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/include/linux/clk-provider.h -+++ b/include/linux/clk-provider.h -@@ -932,12 +932,26 @@ struct clk *clk_register_mux_table(struc - __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ - (parent_data), (flags), (reg), (shift), \ - BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) -+#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ -+ (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ - shift, width, clk_mux_flags, lock) \ - __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ - (parent_names), NULL, NULL, (flags), (reg), \ - (shift), BIT((width)) - 1, (clk_mux_flags), \ - NULL, (lock)) -+#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ -+ NULL, (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - - int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, - unsigned int val); diff --git a/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch b/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch deleted file mode 100644 index 6c5f5ea96b..0000000000 --- a/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 17 Feb 2022 22:43:34 +0100 -Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API - -Convert the driver to parent data API. From the Documentation pll8_vote -and pxo should be declared in the DTS so fw_name can be used instead of -parent_names. Name is still used to save regression on old definition. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/kpss-xcc.c | 26 +++++++++----------------- - 1 file changed, 9 insertions(+), 17 deletions(-) - ---- a/drivers/clk/qcom/kpss-xcc.c -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -12,9 +12,9 @@ - #include - #include - --static const char *aux_parents[] = { -- "pll8_vote", -- "pxo", -+static const struct clk_parent_data aux_parents[] = { -+ { .name = "pll8_vote", .fw_name = "pll8_vote" }, -+ { .name = "pxo", .fw_name = "pxo" }, - }; - - static unsigned int aux_parent_map[] = { -@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t - static int kpss_xcc_driver_probe(struct platform_device *pdev) - { - const struct of_device_id *id; -- struct clk *clk; - struct resource *res; - void __iomem *base; -+ struct clk_hw *hw; - const char *name; - - id = of_match_device(kpss_xcc_match_table, &pdev->dev); -@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct - base += 0x28; - } - -- clk = clk_register_mux_table(&pdev->dev, name, aux_parents, -- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, -- 0, aux_parent_map, NULL); -+ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, -+ ARRAY_SIZE(aux_parents), 0, -+ base, 0, 0x3, -+ 0, aux_parent_map, NULL); - -- platform_set_drvdata(pdev, clk); -- -- return PTR_ERR_OR_ZERO(clk); --} -- --static int kpss_xcc_driver_remove(struct platform_device *pdev) --{ -- clk_unregister_mux(platform_get_drvdata(pdev)); -- return 0; -+ return PTR_ERR_OR_ZERO(hw); - } - - static struct platform_driver kpss_xcc_driver = { - .probe = kpss_xcc_driver_probe, -- .remove = kpss_xcc_driver_remove, - .driver = { - .name = "kpss-xcc", - .of_match_table = kpss_xcc_match_table, diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch new file mode 100644 index 0000000000..a15a723029 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch @@ -0,0 +1,46 @@ +From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 12 Apr 2022 16:48:39 +0200 +Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table + API + +Introduce (devm_)hw_register_mux_parent_data_table new API. We have +basic support for clk_register_mux using parent_data but we lack any API +to provide a custom parent_map. Add these 2 new API to correctly handle +these special configuration instead of using the generic +__(devm_)clk_hw_register_mux API. + +Signed-off-by: Christian Marangi +--- + include/linux/clk-provider.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -932,12 +932,26 @@ struct clk *clk_register_mux_table(struc + __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ + (parent_data), (flags), (reg), (shift), \ + BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) ++#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ ++ num_parents, flags, reg, shift, \ ++ width, clk_mux_flags, table, \ ++ lock) \ ++ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ ++ (parent_data), (flags), (reg), (shift), \ ++ BIT((width)) - 1, (clk_mux_flags), table, (lock)) + #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ + shift, width, clk_mux_flags, lock) \ + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ + (parent_names), NULL, NULL, (flags), (reg), \ + (shift), BIT((width)) - 1, (clk_mux_flags), \ + NULL, (lock)) ++#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ ++ num_parents, flags, reg, shift, \ ++ width, clk_mux_flags, table, \ ++ lock) \ ++ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ ++ NULL, (parent_data), (flags), (reg), (shift), \ ++ BIT((width)) - 1, (clk_mux_flags), table, (lock)) + + int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, + unsigned int val); diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch new file mode 100644 index 0000000000..6c5f5ea96b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch @@ -0,0 +1,70 @@ +From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 17 Feb 2022 22:43:34 +0100 +Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API + +Convert the driver to parent data API. From the Documentation pll8_vote +and pxo should be declared in the DTS so fw_name can be used instead of +parent_names. Name is still used to save regression on old definition. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/kpss-xcc.c | 26 +++++++++----------------- + 1 file changed, 9 insertions(+), 17 deletions(-) + +--- a/drivers/clk/qcom/kpss-xcc.c ++++ b/drivers/clk/qcom/kpss-xcc.c +@@ -12,9 +12,9 @@ + #include + #include + +-static const char *aux_parents[] = { +- "pll8_vote", +- "pxo", ++static const struct clk_parent_data aux_parents[] = { ++ { .name = "pll8_vote", .fw_name = "pll8_vote" }, ++ { .name = "pxo", .fw_name = "pxo" }, + }; + + static unsigned int aux_parent_map[] = { +@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t + static int kpss_xcc_driver_probe(struct platform_device *pdev) + { + const struct of_device_id *id; +- struct clk *clk; + struct resource *res; + void __iomem *base; ++ struct clk_hw *hw; + const char *name; + + id = of_match_device(kpss_xcc_match_table, &pdev->dev); +@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct + base += 0x28; + } + +- clk = clk_register_mux_table(&pdev->dev, name, aux_parents, +- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, +- 0, aux_parent_map, NULL); ++ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, ++ ARRAY_SIZE(aux_parents), 0, ++ base, 0, 0x3, ++ 0, aux_parent_map, NULL); + +- platform_set_drvdata(pdev, clk); +- +- return PTR_ERR_OR_ZERO(clk); +-} +- +-static int kpss_xcc_driver_remove(struct platform_device *pdev) +-{ +- clk_unregister_mux(platform_get_drvdata(pdev)); +- return 0; ++ return PTR_ERR_OR_ZERO(hw); + } + + static struct platform_driver kpss_xcc_driver = { + .probe = kpss_xcc_driver_probe, +- .remove = kpss_xcc_driver_remove, + .driver = { + .name = "kpss-xcc", + .of_match_table = kpss_xcc_match_table, -- cgit v1.2.3