From 3b88f74bbe9134465a84234e1e7400af585f8c2b Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 17 Jul 2017 22:48:31 +0200 Subject: sunxi: Backport patches from kernel 4.11 for A64 This backports some more patches from kernel 4.11 adding more devices to the device tree of the A64 SoC. Signed-off-by: Hauke Mehrtens --- ...4-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch (limited to 'target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch') diff --git a/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch b/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch new file mode 100644 index 0000000000..0d7803775e --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch @@ -0,0 +1,29 @@ +From 0d98479738b950e30bb4f782d60099d44076ad67 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 5 Apr 2017 22:30:34 +0800 +Subject: arm64: allwinner: a64: add pmu0 regs for USB PHY + +The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI +controller pair that can be connected to the PHY0. + +Add the MMIO region for PHY node. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -184,8 +184,10 @@ + usbphy: phy@01c19400 { + compatible = "allwinner,sun50i-a64-usb-phy"; + reg = <0x01c19400 0x14>, ++ <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", ++ "pmu0", + "pmu1"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; -- cgit v1.2.3