From 3f3586a06d27cb6eeab1102e3858b47a1c902ad8 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 12:59:07 +0800 Subject: rockchip: add Orange Pi R1 Plus LTS support The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise identical to OrangePi R1 Plus. Tested-by: Volkan Yetik Signed-off-by: Tianling Shen (cherry picked from commit 32d5921b8b5508a99680ecf1626667517c2cbdb8) [Removed patches for kernel 6.1] Signed-off-by: Tianling Shen --- ...rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch (limited to 'target/linux/rockchip/patches-5.15') diff --git a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 0000000000..cedf28dc79 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,71 @@ +From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 25 Mar 2023 15:40:22 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS + +The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with +the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise +identical to OrangePi R1 Plus. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ + 2 files changed, 41 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,40 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021-2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ ++ motorcomm,clk-out-frequency-hz = <125000000>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; -- cgit v1.2.3