From 2ce5ad745df2d33c15ca20f267292e3cd761dc22 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sun, 30 Aug 2009 19:15:58 +0000 Subject: [ramips] share common INTC code git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17440 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../ramips/files/arch/mips/ralink/common/Makefile | 10 +++ .../ramips/files/arch/mips/ralink/common/intc.c | 98 ++++++++++++++++++++++ 2 files changed, 108 insertions(+) create mode 100644 target/linux/ramips/files/arch/mips/ralink/common/Makefile create mode 100644 target/linux/ramips/files/arch/mips/ralink/common/intc.c (limited to 'target/linux/ramips/files/arch/mips/ralink/common') diff --git a/target/linux/ramips/files/arch/mips/ralink/common/Makefile b/target/linux/ramips/files/arch/mips/ralink/common/Makefile new file mode 100644 index 0000000000..2816a67089 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/ralink/common/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the Ralink common stuff +# +# Copyright (C) 2009 Gabor Juhos +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := intc.o diff --git a/target/linux/ramips/files/arch/mips/ralink/common/intc.c b/target/linux/ramips/files/arch/mips/ralink/common/intc.c new file mode 100644 index 0000000000..da3ecd4664 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/ralink/common/intc.c @@ -0,0 +1,98 @@ +/* + * Ralink SoC Interrupt controller routines + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* INTC register offsets */ +#define INTC_REG_STATUS0 0x00 +#define INTC_REG_STATUS1 0x04 +#define INTC_REG_TYPE 0x20 +#define INTC_REG_RAW_STATUS 0x30 +#define INTC_REG_ENABLE 0x34 +#define INTC_REG_DISABLE 0x38 + +#define INTC_INT_GLOBAL BIT(31) +#define INTC_IRQ_COUNT 32 + +static unsigned int ramips_intc_irq_base; +static void __iomem *ramips_intc_base; + +static inline void ramips_intc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_intc_base + reg); +} + +static inline u32 ramips_intc_rr(unsigned reg) +{ + return __raw_readl(ramips_intc_base + reg); +} + +static void ramips_intc_irq_unmask(unsigned int irq) +{ + irq -= ramips_intc_irq_base; + ramips_intc_wr((1 << irq), INTC_REG_ENABLE); +} + +static void ramips_intc_irq_mask(unsigned int irq) +{ + irq -= ramips_intc_irq_base; + ramips_intc_wr((1 << irq), INTC_REG_DISABLE); +} + +static struct irq_chip ramips_intc_irq_chip = { + .name = "INTC", + .unmask = ramips_intc_irq_unmask, + .mask = ramips_intc_irq_mask, + .mask_ack = ramips_intc_irq_mask, +}; + +static struct irqaction ramips_intc_irqaction = { + .handler = no_action, + .name = "cascade [INTC]", +}; + +void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq, + unsigned irq_base) +{ + int i; + + ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE); + ramips_intc_irq_base = irq_base; + + /* disable all interrupts */ + ramips_intc_wr(~0, INTC_REG_DISABLE); + + /* route all INTC interrupts to MIPS HW0 interrupt */ + ramips_intc_wr(0, INTC_REG_TYPE); + + for (i = ramips_intc_irq_base; + i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) { + set_irq_chip_and_handler(i, &ramips_intc_irq_chip, + handle_level_irq); + } + + setup_irq(irq, &ramips_intc_irqaction); + ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE); +} + +u32 ramips_intc_get_status(void) +{ + return ramips_intc_rr(INTC_REG_STATUS0); +} -- cgit v1.2.3