From e382d2c7e615dfbdfeca88b6a66fff5eabd8cc61 Mon Sep 17 00:00:00 2001
From: John Crispin <john@openwrt.org>
Date: Tue, 8 Oct 2013 21:10:15 +0000
Subject: ralink: add support for the mt7530 eval board

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 38345
---
 target/linux/ramips/dts/MT7620a.dts        |  16 ++---
 target/linux/ramips/dts/MT7620a_MT7530.dts | 107 +++++++++++++++++++++++++++++
 target/linux/ramips/dts/mt7620a.dtsi       |  24 +++++--
 3 files changed, 134 insertions(+), 13 deletions(-)
 create mode 100644 target/linux/ramips/dts/MT7620a_MT7530.dts

(limited to 'target/linux/ramips/dts')

diff --git a/target/linux/ramips/dts/MT7620a.dts b/target/linux/ramips/dts/MT7620a.dts
index 3351f20b17..0a5999bac9 100644
--- a/target/linux/ramips/dts/MT7620a.dts
+++ b/target/linux/ramips/dts/MT7620a.dts
@@ -47,7 +47,7 @@
 	pinctrl {
 		state_default: pinctrl0 {
 			gpio {
-				ralink,group = "mdio", "i2c", "uartf";
+				ralink,group = "i2c", "uartf";
 				ralink,function = "gpio";
 			};
 		};
@@ -56,16 +56,19 @@
 	ethernet@10100000 {
 		status = "okay";
 		
+		pinctrl-names = "default";
+		pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
+
+		ralink,port-map = "llllw";
+
 		port@4 {
-			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-			reg = <4>;
+			status = "okay";
 			phy-mode = "rgmii";
 			phy-handle = <&phy4>;
 		};
 
 		port@5 {
-			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-			reg = <5>;
+			status = "okay";
 			phy-mode = "rgmii";
 			phy-handle = <&phy5>;
 		};
@@ -87,9 +90,6 @@
 
 	gsw@10110000 {
 		ralink,port4 = "gmac";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&ephy_pins>;
 	};
 
 	sdhci@10130000 {
diff --git a/target/linux/ramips/dts/MT7620a_MT7530.dts b/target/linux/ramips/dts/MT7620a_MT7530.dts
new file mode 100644
index 0000000000..fcd1219e68
--- /dev/null
+++ b/target/linux/ramips/dts/MT7620a_MT7530.dts
@@ -0,0 +1,107 @@
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+	compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+	model = "Ralink MT7620a + MT7530 evaluation board";
+
+	palmbus@10000000 {
+		spi@b00 {
+			status = "okay";
+		
+			m25p80@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "s25fl064k";
+				reg = <0 0>;
+				linux,modalias = "m25p80", "s25fl064k";
+				spi-max-frequency = <10000000>;
+
+				partition@0 {
+					label = "u-boot";
+					reg = <0x0 0x30000>;
+					read-only;
+				};
+
+				partition@30000 {
+					label = "u-boot-env";
+					reg = <0x30000 0x10000>;
+					read-only;
+				};
+
+				factory: partition@40000 {
+					label = "factory";
+					reg = <0x40000 0x10000>;
+					read-only;
+				};
+
+				partition@50000 {
+					label = "firmware";
+					reg = <0x50000 0x7b0000>;
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		state_default: pinctrl0 {
+			gpio {
+				ralink,group = "i2c", "uartf";
+				ralink,function = "gpio";
+			};
+		};
+	};
+
+	ethernet@10100000 {
+		status = "okay";
+		
+		pinctrl-names = "default";
+		pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
+		
+		ralink,port-map = "llllw";
+
+		port@5 {
+			status = "okay";
+			ralink,fixed-link = <1000 1 1 1>;
+			phy-mode = "rgmii";
+		};
+
+		mdio-bus {
+			status = "okay";
+
+			phy0: ethernet-phy@0 {
+				reg = <0>;
+				phy-mode = "rgmii";
+			};
+			phy1: ethernet-phy@1 {
+				reg = <1>;
+				phy-mode = "rgmii";
+			};
+			phy2: ethernet-phy@2 {
+				reg = <2>;
+				phy-mode = "rgmii";
+			};
+			phy3: ethernet-phy@3 {
+				reg = <3>;
+				phy-mode = "rgmii";
+			};
+			phy4: ethernet-phy@4 {
+				reg = <4>;
+				phy-mode = "rgmii";
+			};
+			phy1f: ethernet-phy@1f {
+				reg = <0x1f>;
+				phy-mode = "rgmii";
+			};
+		};
+	};
+
+	gsw@10110000 {
+		ralink,port4 = "gmac";
+	};
+
+	pcie@10140000 {
+		status = "okay";
+	};
+};
diff --git a/target/linux/ramips/dts/mt7620a.dtsi b/target/linux/ramips/dts/mt7620a.dtsi
index fa7cea6de6..4ad0a7c2a9 100644
--- a/target/linux/ramips/dts/mt7620a.dtsi
+++ b/target/linux/ramips/dts/mt7620a.dtsi
@@ -298,13 +298,13 @@
 			};
 		};
 		rgmii1_pins: rgmii1 {
-			mdio {
+			rgmii1 {
 				ralink,group = "rgmii1";
 				ralink,function = "rgmii1";
 			};
 		};
 		rgmii2_pins: rgmii2 {
-			mdio {
+			rgmii2 {
 				ralink,group = "rgmii2";
 				ralink,function = "rgmii2";
 			};
@@ -333,14 +333,28 @@
 		interrupt-parent = <&cpuintc>;
 		interrupts = <5>;
 
+		resets = <&rstctrl 21 &rstctrl 23>;
+		reset-names = "fe", "esw";
+
+		port@4 {
+			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+			reg = <4>;
+
+			status = "disabled";
+		};
+
+		port@5 {
+			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+			reg = <5>;
+
+			status = "disabled";
+		};
+
 		mdio-bus {
 			#address-cells = <1>;
 			#size-cells = <0>;
 
 			status = "disabled";
-
-			pinctrl-names = "default";
-			pinctrl-0 = <&mdio_pins>;
 		};
 	};
 
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