From 7196ca1d497b6f0727a285bc3ecd41d54aff3a81 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Wed, 3 Jul 2019 23:22:28 +0200 Subject: ramips/mt7621: Name DTS files based on scheme As introduced with ath79, DTS files for ramips will now be labelled soc_vendor_device.dts(i). With this change, DTS files can be selected automatically without further manual links. Signed-off-by: Adrian Schmutzler --- target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts | 197 +++++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts (limited to 'target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts') diff --git a/target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts b/target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts new file mode 100644 index 0000000000..f40c4f733f --- /dev/null +++ b/target/linux/ramips/dts/mt7621_mikrotik_rbm33g.dts @@ -0,0 +1,197 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +#include +#include + +/ { + compatible = "mikrotik,rbm33g", "mediatek,mt7621-soc"; + model = "MikroTik RouterBOARD M33G"; + + aliases { + led-boot = &led_usr; + led-failsafe = &led_usr; + led-running = &led_usr; + led-upgrade = &led_usr; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led_usr: usr { + label = "rbm33g:green:usr"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + res { + label = "res"; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pcie0_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "pcie0_vcc"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + pcie1_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "pcie1_vcc"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + pcie2_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "pcie2_vcc"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + usb_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "usb_vcc"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + + +&spi0 { + status = "okay"; + + w25q40@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3125000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RouterBoot"; + reg = <0x0 0x40000>; + read-only; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader1"; + reg = <0x0 0xf000>; + read-only; + }; + + hard_config: partition@f000 { + label = "hard_config"; + reg = <0xf000 0x1000>; + read-only; + }; + + partition@10000 { + label = "bootloader2"; + reg = <0x10000 0xf000>; + read-only; + }; + + partition@20000 { + label = "soft_config"; + reg = <0x20000 0x1000>; + }; + + partition@30000 { + label = "bios"; + reg = <0x30000 0x1000>; + read-only; + }; + }; + }; + }; + + w25q128@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + // XXX empiric value to obtain actual 10MHz SCK at the chip + spi-max-frequency = <3125000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + // Region <0x0 0x40000> seems reserved by OEM + + partition@40000 { + compatible = "mikrotik,minor"; + label = "firmware"; + reg = <0x040000 0xFC0000>; + }; + }; + }; +}; + +ðernet { + mtd-mac-address = <&hard_config 0x0010>; + mtd-mac-address-increment = <1>; +}; + + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart2", "wdt"; + ralink,function = "gpio"; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&i2c { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; -- cgit v1.2.3