From 92558d67a463bfbb351d30e28648de03b635f024 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 6 Sep 2007 16:27:37 +0000 Subject: strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX__ becomes CONFIG_TARGET_, same for profiles. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/pxa-2.6/Makefile | 25 - target/linux/pxa-2.6/config/default | 390 ---------- target/linux/pxa-2.6/image | 1 - target/linux/pxa-2.6/patches/000-cpufreq.patch | 533 ------------- target/linux/pxa-2.6/patches/001-pm.patch | 869 ---------------------- target/linux/pxa-2.6/patches/002-usb_gadget.patch | 58 -- target/linux/pxa-2.6/patches/004-skbuf_hack.patch | 10 - target/linux/pxa-2.6/patches/005-mtd.patch | 111 --- 8 files changed, 1997 deletions(-) delete mode 100644 target/linux/pxa-2.6/Makefile delete mode 100644 target/linux/pxa-2.6/config/default delete mode 120000 target/linux/pxa-2.6/image delete mode 100644 target/linux/pxa-2.6/patches/000-cpufreq.patch delete mode 100644 target/linux/pxa-2.6/patches/001-pm.patch delete mode 100644 target/linux/pxa-2.6/patches/002-usb_gadget.patch delete mode 100644 target/linux/pxa-2.6/patches/004-skbuf_hack.patch delete mode 100644 target/linux/pxa-2.6/patches/005-mtd.patch (limited to 'target/linux/pxa-2.6') diff --git a/target/linux/pxa-2.6/Makefile b/target/linux/pxa-2.6/Makefile deleted file mode 100644 index 3e0e6cd3b3..0000000000 --- a/target/linux/pxa-2.6/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=pxa -BOARDNAME:=PXA -FEATURES:=jffs2 broken - -LINUX_VERSION:=2.6.21.5 - -define Target/Description - Stub for boards based on intel PXA -endef - -include $(INCLUDE_DIR)/kernel-build.mk - -# include the profiles --include profiles/*.mk - -$(eval $(call BuildKernel)) diff --git a/target/linux/pxa-2.6/config/default b/target/linux/pxa-2.6/config/default deleted file mode 100644 index e288e4273b..0000000000 --- a/target/linux/pxa-2.6/config/default +++ /dev/null @@ -1,390 +0,0 @@ -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APM is not set -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91RM9200 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -CONFIG_ARCH_LUBBOCK=y -CONFIG_ARCH_MTD_XIP=y -# CONFIG_ARCH_OMAP is not set -CONFIG_ARCH_PXA=y -# CONFIG_ARCH_PXA_IDP is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARM=y -# CONFIG_ARM_THUMB is not set -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -# CONFIG_ATM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_BONDING is not set -# CONFIG_BRIDGE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BT is not set -# CONFIG_CIFS is not set -# CONFIG_CLS_U32_MARK is not set -# CONFIG_CLS_U32_PERF is not set -CONFIG_CMDLINE="root=/dev/mtdblock0 rootfstype=jffs2 console=tty0 console=ttyS2,115200 mem=16M" -# CONFIG_CONFIGFS_FS is not set -CONFIG_CONNECTOR=m -CONFIG_CPU_32=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEBUG is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_PXA=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_XSCALE=y -CONFIG_CRAMFS=y -# CONFIG_CRC16 is not set -CONFIG_CRC_CCITT=y -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_USER is not set -CONFIG_DMABOUNCE=y -CONFIG_DNOTIFY=y -CONFIG_DUMMY_CONSOLE=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_FIRMWARE_EDID=y -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MODE_HELPERS is not set -CONFIG_FB_PXA=y -# CONFIG_FB_PXA_PARAMETERS is not set -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_TILEBLITTING=y -# CONFIG_FB_VIRTUAL is not set -CONFIG_FONTS=y -# CONFIG_FONT_10x18 is not set -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_8x16 is not set -CONFIG_FONT_8x8=y -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_SUN8x16 is not set -CONFIG_FORCE_MAX_ZONEORDER=9 -# CONFIG_FPE_FASTFPE is not set -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_POINTER=y -CONFIG_GTEK_LCD=y -# CONFIG_HAMRADIO is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HOSTAP is not set -CONFIG_HW_CONSOLE=y -CONFIG_HZ=100 -CONFIG_I2C=y -# CONFIG_I2C_ALGOBIT is not set -CONFIG_I2C_ALGOPCA=y -# CONFIG_I2C_ALGOPCF is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PCA_ISA is not set -CONFIG_I2C_PXA=y -# CONFIG_I2C_PXA_SLAVE is not set -# CONFIG_I2C_STUB is not set -# CONFIG_IDE is not set -# CONFIG_IEEE80211 is not set -# CONFIG_IKCONFIG is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_INOTIFY is not set -CONFIG_INPUT=y -# CONFIG_INPUT_EVDEV is not set -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=y -CONFIG_IP_NF_IRC=y -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -CONFIG_IP_NF_MATCH_DSCP=m -# CONFIG_IP_NF_MATCH_HASHLIMIT is not set -CONFIG_IP_NF_NAT_FTP=y -CONFIG_IP_NF_NAT_IRC=y -CONFIG_IP_NF_TARGET_DSCP=m -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_SAME is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -# CONFIG_ISO9660_FS is not set -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFS_FS is not set -CONFIG_KEYBOARD_ATKBD=y -CONFIG_KEYBOARD_GTEK=y -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KMOD=y -# CONFIG_LEDS is not set -# CONFIG_LIBCRC32C is not set -# CONFIG_LLC2 is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_MACH_GTEK=y -# CONFIG_MACH_LOGICPD_PXA270 is not set -# CONFIG_MACH_MAINSTONE is not set -# CONFIG_MINIX_FS is not set -# CONFIG_MSDOS_FS is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -# CONFIG_MTD_CFI_AMDSTD is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_CONCAT=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_LUBBOCK=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_SHARP_SL is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_XIP is not set -CONFIG_NET_DIVERT=y -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_NET_KEY is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_WIRELESS_RTNETLINK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_NLS is not set -# CONFIG_NO_IDLE_HZ is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NVRAM is not set -CONFIG_OBSOLETE_INTERMODULE=y -# CONFIG_PARTITION_ADVANCED is not set -# CONFIG_PCMCIA is not set -# CONFIG_PCCARD is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_LEGACY=y -CONFIG_PPP=y -# CONFIG_PPPOE is not set -CONFIG_PPP_ASYNC=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -# CONFIG_PPP_MPPE is not set -CONFIG_PPP_SYNC_TTY=y -CONFIG_PXA25x=y -# CONFIG_PXA_SHARPSL is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -CONFIG_RTC_DRV_SA1100=y -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_X1205 is not set -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_LIB=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_SA1111=y -# CONFIG_SCSI is not set -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_SA1111 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SMB_FS is not set -CONFIG_SND=y -CONFIG_SND_AC97_BUS=y -CONFIG_SND_AC97_CODEC=y -CONFIG_SND_DUMMY=m -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PXA2XX_AC97=y -CONFIG_SND_PXA2XX_PCM=y -CONFIG_SND_SEQUENCER=y -# CONFIG_SND_SEQUENCER_OSS is not set -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_TIMER=y -# CONFIG_SND_VIRMIDI is not set -CONFIG_SOUND=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_SQUASHFS is not set -# CONFIG_TELCLOCK is not set -# CONFIG_TUN is not set -# CONFIG_UDF_FS is not set -CONFIG_UID16=y -# CONFIG_UNWIND_INFO is not set -# CONFIG_USB is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_FILE_STORAGE is not set -CONFIG_USB_GADGET=m -CONFIG_USB_GADGETFS=m -# CONFIG_USB_GADGET_AT91 is not set -CONFIG_USB_GADGET_DEBUG_FILES=y -# CONFIG_USB_GADGET_DUALSPEED is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_OMAP is not set -CONFIG_USB_GADGET_PXA2XX=y -CONFIG_USB_GADGET_SELECTED=y -CONFIG_USB_G_SERIAL=m -CONFIG_USB_PXA2XX=m -# CONFIG_USB_PXA2XX_SMALL is not set -# CONFIG_USB_ZERO is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFAT_FS is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_VLAN_8021Q is not set -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_WATCHDOG is not set -# CONFIG_XFS_FS is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_XSCALE_PMU=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/pxa-2.6/image b/target/linux/pxa-2.6/image deleted file mode 120000 index a96fdd0abb..0000000000 --- a/target/linux/pxa-2.6/image +++ /dev/null @@ -1 +0,0 @@ -../generic-2.6/image/ \ No newline at end of file diff --git a/target/linux/pxa-2.6/patches/000-cpufreq.patch b/target/linux/pxa-2.6/patches/000-cpufreq.patch deleted file mode 100644 index 3cb6676b41..0000000000 --- a/target/linux/pxa-2.6/patches/000-cpufreq.patch +++ /dev/null @@ -1,533 +0,0 @@ -diff -Nurbw linux-2.6.17/arch/arm/Kconfig linux-2.6.17-patched/arch/arm/Kconfig ---- linux-2.6.17/arch/arm/Kconfig 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/arch/arm/Kconfig 2006-09-21 14:57:02.000000000 -0700 -@@ -656,7 +656,7 @@ - - endmenu - --if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1) -+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1 || ARCH_PXA) - - menu "CPU Frequency scaling" - -@@ -685,6 +685,13 @@ - - endmenu - -+config CPU_FREQ_PXA -+ bool -+ depends on CPU_FREQ && ARCH_PXA -+ default y -+ select CPU_FREQ_DEFAULT_GOV_USERSPACE -+ select CPU_FREQ_TABLE -+ - endif - - menu "Floating point emulation" -diff -Nurbw linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c ---- linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c 1969-12-31 16:00:00.000000000 -0800 -+++ linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c 2006-09-21 14:57:02.000000000 -0700 -@@ -0,0 +1,324 @@ -+/* -+ * linux/arch/arm/mach-pxa/cpu-pxa.c -+ * -+ * Copyright (C) 2002,2003 Intrinsyc Software -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * History: -+ * 31-Jul-2002 : Initial version [FB] -+ * 29-Jan-2003 : added PXA255 support [FB] -+ * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) -+ * -+ * Note: -+ * This driver may change the memory bus clock rate, but will not do any -+ * platform specific access timing changes... for example if you have flash -+ * memory connected to CS0, you will need to register a platform specific -+ * notifier which will adjust the memory access strobes to maintain a -+ * minimum strobe width. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+ -+#ifdef DEBUG -+ static unsigned int freq_debug = DEBUG; -+ module_param(freq_debug, int, 0); -+ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); -+#else -+ #define freq_debug 0 -+#endif -+ -+typedef struct -+{ -+ unsigned int khz; -+ unsigned int membus; -+ unsigned int cccr; -+ unsigned int div2; -+} pxa_freqs_t; -+ -+/* Define the refresh period in mSec for the SDRAM and the number of rows */ -+#define SDRAM_TREF 64 /* standard 64ms SDRAM */ -+#define SDRAM_ROWS 2048 /* 64MB=8192 32MB=4096 */ -+#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32)) -+ -+#define CCLKCFG_TURBO 0x1 -+#define CCLKCFG_FCS 0x2 -+#define PXA25x_MIN_FREQ 99533 -+#define PXA25x_MAX_FREQ 530842 -+#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) -+#define MDREFR_DRI_MASK 0xFFF -+ -+ -+/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ -+static pxa_freqs_t pxa255_run_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99533, 99533, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ -+ {132710, 132710, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ -+ {199066, 99533, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ -+ {265421, 132710, 0x143, 0}, /* run=265, turbo=265, PXbus=133, SDRAM=133 */ -+ {331776, 165888, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ -+ {398131, 99533, 0x161, 0}, /* run=398, turbo=398, PXbus=99, SDRAM=99 */ -+ {398131, 132710, 0x1c3, 0}, /* run=265, turbo=398, PXbus=133, SDRAM=133 */ -+ {530842, 132710, 0x163, 0}, /* run=531, turbo=531, PXbus=133, SDRAM=133 */ -+ {0,} -+}; -+#define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1]; -+ -+/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ -+static pxa_freqs_t pxa255_turbo_freqs[] = -+{ -+ /* CPU MEMBUS CCCR DIV2*/ -+ { 99533, 99533, 0x121, 1}, /* run=99, turbo= 99, PXbus=99, SDRAM=50 */ -+ {149299, 99533, 0x1a1, 0}, /* run=99, turbo=149, PXbus=99, SDRAM=99 */ -+ {199066, 99533, 0x221, 0}, /* run=99, turbo=199, PXbus=99, SDRAM=99 */ -+ {298598, 99533, 0x321, 0}, /* run=99, turbo=299, PXbus=99, SDRAM=99 */ -+ {398131, 99533, 0x241, 1}, /* run=199, turbo=398, PXbus=99, SDRAM=50 */ -+ {0,} -+}; -+#define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t)) -+ -+static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; -+ -+extern unsigned get_clk_frequency_khz(int info); -+ -+/* find a valid frequency point */ -+static int pxa_verify_policy(struct cpufreq_policy *policy) -+{ -+ int ret; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freqs_table = pxa255_run_freq_table; -+ } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ } else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ ret=cpufreq_frequency_table_verify(policy, pxa_freqs_table); -+ -+ if(freq_debug) { -+ printk("Verified CPU policy: %dKhz min to %dKhz max\n", -+ policy->min, policy->max); -+ } -+ -+ return ret; -+} -+ -+static int pxa_set_target(struct cpufreq_policy *policy, -+ unsigned int target_freq, -+ unsigned int relation) -+{ -+ int idx; -+ cpumask_t cpus_allowed; -+ int cpu = policy->cpu; -+ struct cpufreq_freqs freqs; -+ pxa_freqs_t *pxa_freq_settings; -+ struct cpufreq_frequency_table *pxa_freqs_table; -+ unsigned long flags; -+ unsigned int unused; -+ unsigned int preset_mdrefr, postset_mdrefr; -+ void *ramstart; -+ -+ /* -+ * Save this threads cpus_allowed mask. -+ */ -+ cpus_allowed = current->cpus_allowed; -+ -+ /* -+ * Bind to the specified CPU. When this call returns, -+ * we should be running on the right CPU. -+ */ -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* Get the current policy */ -+ if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) { -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ }else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { -+ pxa_freq_settings = pxa255_turbo_freqs; -+ pxa_freqs_table = pxa255_turbo_freq_table; -+ }else { -+ printk("CPU PXA: Unknown policy found. " -+ "Using CPUFREQ_POLICY_PERFORMANCE\n"); -+ pxa_freq_settings = pxa255_run_freqs; -+ pxa_freqs_table = pxa255_run_freq_table; -+ } -+ -+ /* Lookup the next frequency */ -+ if (cpufreq_frequency_table_target(policy, pxa_freqs_table, -+ target_freq, relation, &idx)) { -+ return -EINVAL; -+ } -+ -+ freqs.old = policy->cur; -+ freqs.new = pxa_freq_settings[idx].khz; -+ freqs.cpu = policy->cpu; -+ if(freq_debug) { -+ printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", -+ freqs.new/1000, (pxa_freq_settings[idx].div2) ? -+ (pxa_freq_settings[idx].membus/2000) : -+ (pxa_freq_settings[idx].membus/1000)); -+ } -+ -+ ramstart = phys_to_virt(0xa0000000); -+ -+ /* -+ * Tell everyone what we're about to do... -+ * you should add a notify client with any platform specific -+ * Vcc changing capability -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); -+ -+ /* Calculate the next MDREFR. If we're slowing down the SDRAM clock -+ * we need to preset the smaller DRI before the change. If we're speeding -+ * up we need to set the larger DRI value after the change. -+ */ -+ preset_mdrefr = postset_mdrefr = MDREFR; -+ if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { -+ preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ } -+ postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | -+ MDREFR_DRI(pxa_freq_settings[idx].membus); -+ -+ /* If we're dividing the memory clock by two for the SDRAM clock, this -+ * must be set prior to the change. Clearing the divide must be done -+ * after the change. -+ */ -+ if(pxa_freq_settings[idx].div2) { -+ preset_mdrefr |= MDREFR_DB2_MASK; -+ postset_mdrefr |= MDREFR_DB2_MASK; -+ } else { -+ postset_mdrefr &= ~MDREFR_DB2_MASK; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Set new the CCCR */ -+ CCCR = pxa_freq_settings[idx].cccr; -+ -+ __asm__ __volatile__(" \ -+ ldr r4, [%1] ; /* load MDREFR */ \ -+ b 2f ; \ -+ .align 5 ; \ -+1: \ -+ str %4, [%1] ; /* preset the MDREFR */ \ -+ mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \ -+ str %5, [%1] ; /* postset the MDREFR */ \ -+ \ -+ b 3f ; \ -+2: b 1b ; \ -+3: nop ; \ -+ " -+ : "=&r" (unused) -+ : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), \ -+ "r" (preset_mdrefr), "r" (postset_mdrefr) -+ : "r4", "r5"); -+ local_irq_restore(flags); -+ -+ /* -+ * Restore the CPUs allowed mask. -+ */ -+ set_cpus_allowed(current, cpus_allowed); -+ -+ /* -+ * Tell everyone what we've just done... -+ * you should add a notify client with any platform specific -+ * SDRAM refresh timer adjustments -+ */ -+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); -+ -+ return 0; -+} -+ -+static int pxa_cpufreq_init(struct cpufreq_policy *policy) -+{ -+ cpumask_t cpus_allowed; -+ unsigned int cpu = policy->cpu; -+ int i; -+ -+ cpus_allowed = current->cpus_allowed; -+ -+ set_cpus_allowed(current, cpumask_of_cpu(cpu)); -+ BUG_ON(cpu != smp_processor_id()); -+ -+ /* set default policy and cpuinfo */ -+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR; -+ policy->policy = CPUFREQ_POLICY_PERFORMANCE; -+ policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; -+ policy->cpuinfo.min_freq = PXA25x_MIN_FREQ; -+ policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ -+ policy->cur = get_clk_frequency_khz(0); /* current freq */ -+ policy->min = policy->max = policy->cur; -+ -+ /* Generate the run cpufreq_frequency_table struct */ -+ for(i=0;i - #include --#include --#include -+#include -+#include -+#include -+#include -+#include - #include --#include - - #include - #include - #include --#include -+#include -+#include - #include - #include - #include - -+/**/ -+#include -+/**/ -+//kirti -+#include -+//kirti~ - - /* - * Debug macros - */ --#undef DEBUG -+#define DEBUG -+ -+extern void pxa_cpu_suspend(void); -+extern void pxa_cpu_resume(void); -+ -+int pm_pwronoff; -+/*Angelia Additions */ -+int pm_pedr=0; -+EXPORT_SYMBOL(pm_pwronoff); -+EXPORT_SYMBOL(pm_pedr); -+ - - #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x - #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - --#define RESTORE_GPLEVEL(n) do { \ -- GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ -- GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ --} while (0) -- - /* - * List of global PXA peripheral registers to preserve. - * More ones like CP and general purpose register values are preserved -@@ -46,97 +61,405 @@ - */ - enum { SLEEP_SAVE_START = 0, - -- SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, -- SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, -- SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, -- SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, -- SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, -- -- SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, -- SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, -- SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, -- SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, -+ SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER, -+ SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3, - -- SLEEP_SAVE_PSTR, -+ SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, -+ SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, -+ SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, -+ SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L, -+ SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U, -+ -+ SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR, -+ SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR, -+ SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,SLEEP_SAVE_FFFCR, -+ -+ SLEEP_SAVE_STIER, SLEEP_SAVE_STLCR, SLEEP_SAVE_STMCR, -+ SLEEP_SAVE_STSPR, SLEEP_SAVE_STISR, -+ SLEEP_SAVE_STDLL, SLEEP_SAVE_STDLH, -+ -+ SLEEP_SAVE_BTIER, SLEEP_SAVE_BTLCR, SLEEP_SAVE_BTMCR, -+ SLEEP_SAVE_BTSPR, SLEEP_SAVE_BTISR, -+ SLEEP_SAVE_BTDLL, SLEEP_SAVE_BTDLH, - - SLEEP_SAVE_ICMR, - SLEEP_SAVE_CKEN, - --#ifdef CONFIG_PXA27x -- SLEEP_SAVE_MDREFR, -- SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, -- SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, --#endif -+ SLEEP_SAVE_LCCR0, SLEEP_SAVE_LCCR1, SLEEP_SAVE_LCCR2,SLEEP_SAVE_LCCR3, -+ SLEEP_SAVE_TMEDCR, SLEEP_SAVE_FDADR0, SLEEP_SAVE_FSADR0,SLEEP_SAVE_FIDR0,SLEEP_SAVE_FDADR1, -+ SLEEP_SAVE_LDCMD0, -+ -+ SLEEP_SAVE_NSSCR0,SLEEP_SAVE_NSSCR1,SLEEP_SAVE_NSSSR,SLEEP_SAVE_NSSITR,SLEEP_SAVE_NSSDR, -+ SLEEP_SAVE_NSSTO,SLEEP_SAVE_NSSPSP, - -- SLEEP_SAVE_CKSUM, - -+ SLEEP_SAVE_CKSUM, - SLEEP_SAVE_SIZE - }; - -+/**/ -+#define UART_DTR 1 -+#define UART_RTS 2 -+ -+/**/ - --int pxa_pm_enter(suspend_state_t state) -+int pm_do_suspend(void) - { - unsigned long sleep_save[SLEEP_SAVE_SIZE]; - unsigned long checksum = 0; -- struct timespec delta, rtc; - int i; -+ int valbefore,valafter,valafter1; -+ int gpsr0,gpsr1,gpsr2; - extern void pxa_cpu_pm_enter(suspend_state_t state); - --#ifdef CONFIG_IWMMXT -- /* force any iWMMXt context to ram **/ -- iwmmxt_task_disable(NULL); --#endif -+ // YoKu 16Feb06 GPIO Changed -----> -+ -+ PGSR2 |= GPIO_bit(78); -+/* if(GPLR2 & GPIO_bit(78)) // LCD Reset Pin -+ PGSR2 |= GPIO_bit(78); -+ else -+ PGSR2 &= ~GPIO_bit(78); */ -+ GPDR0 &= ~GPIO_bit(0); -+ GPDR0 &= ~GPIO_bit(1); -+ GPDR0 &= ~GPIO_bit(3); //Tushar: 20 apr GPIO3 configured as input -+ GPDR0 &= ~GPIO_bit(2); -+// GPDR0 &= ~GPIO_bit(5); -+// GPDR0 &= ~GPIO_bit(6); -+// GPDR0 &= ~GPIO_bit(7); -+// GPDR0 &= ~GPIO_bit(8); -+ -+ -+// KeyCol pin Status in sleep mode -+ PGSR0 &= ~GPIO_bit(9); //19 -+ PGSR0 &= ~GPIO_bit(10); //20 -+ PGSR0 &= ~GPIO_bit(11); //21 -+ PGSR0 &= ~GPIO_bit(12); //22 -+ PGSR0 &= ~GPIO_bit(13); //23 -+ PGSR0 &= ~GPIO_bit(14); //24 -+ -+ printk("KER_PM: Setting up wakeup sources 26May06\n"); -+ -+ // KeyPad -+ //printk("KER_PM: Uncommented key pad wakeup sources\n"); -+ PWER |= GPIO_bit(5); //11 -+ PWER |= GPIO_bit(6); //12 -+ PWER |= GPIO_bit(7); //13 -+ PWER |= GPIO_bit(8); //14 -+ PFER |= GPIO_bit(5); //11 -+ PFER |= GPIO_bit(6); //12 -+ PFER |= GPIO_bit(7); //13 -+ PFER |= GPIO_bit(8); //14 -+ PRER |= GPIO_bit(5); //11 -+ PRER |= GPIO_bit(6); //12 -+ PRER |= GPIO_bit(7); //13 -+ PRER |= GPIO_bit(8); //14 -+ -+ // USB -+ PWER |= GPIO_bit(3); //6 -+ PFER |= GPIO_bit(3); //6 -+ PRER |= GPIO_bit(3); //6 -+ -+ // PMU -+ PWER |= GPIO_bit(2); //4 -+ PFER |= GPIO_bit(2); //4 -+ PRER |= GPIO_bit(2); //4 -+ -+ // Anup : GSM RI -+ PWER |= GPIO_bit(0); //0 -+ PFER |= GPIO_bit(0); //0 -+ PRER |= GPIO_bit(0); //0 -+ // anup prashant : for gsm reset problem 19 may 2006 -+ //GPDR0 |= GPIO_bit(18); YoKu Commented this line, GPIO18 should be i/p pin to avoid GSM Reset pulse -+ PGSR0 |= GPIO_bit(18); // GSM reset pin -+ PGSR0 |= GPIO_bit(0); // -+ PGSR1 |= GPIO_bit(38); // commneted .18 apr -+ // <----- YoKu -+ -+ // YoKu -----> -+ // When exiting from sleep mode, 10us Low pulse comes on GSM Reset and Pwr pin -+ // to avoid this configure GPIO 18,80 as input pins before going to sleep mode -+ GPDR0 &= ~GPIO_bit(18); -+ //GPDR2 &= ~GPIO_bit(80); -+ // <----- YoKu -+ -+ //kirti for RTC -+ PWER |= PWER_RTC; -+ //kirti cli(); -+ local_irq_disable(); -+ //kirti clf(); -+ local_fiq_disable(); -+ leds_event(led_stop); -+ -+ /* Put Current time into RCNR */ -+ RCNR = xtime.tv_sec; - -- /* preserve current time */ -- rtc.tv_sec = RCNR; -- rtc.tv_nsec = 0; -- save_time_delta(&delta, &rtc); -+ printk("11May2006 KERR: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2); -+ printk("KER_PM_DELAY: SSCR Going to Sleep at RCNR =%d\n\n\n\n\n\n",RCNR); -+ -+ /* -+ * Temporary solution. This won't be necessary once -+ * we move pxa support into the serial driver -+ * Save the FF UART -+ */ -+ -+ // Anup : commented for power saving mode problem -+ printk("\nPM: Why doesnt it prnt?? 26May06\n"); -+ printk("\nPM : GSM Sleep Mode enabled"); -+ -+ -+ FFMCR &= ~UART_RTS; -+ udelay(2000); -+ udelay(2000); -+ FFMCR &= ~UART_DTR ; -+ udelay(2000); -+ -+ udelay(2000); -+ // rupali -+ // Anup : Do not check here -+/* if(!pm_pwronoff) -+ { -+ printk("\nPM : Modem Control Register = %x " , FFMCR); -+ while( FFMSR & 0x00000020) -+ { -+ printk("\nPM : FFFSR = %x " , FFMSR); -+ } -+ } */ -+ udelay(2000); -+ -+//Tushar: 19 apr -+// NSSCR0 &= 0xFFFFFF7F; -+// printk("\nPM: NSSCR0 = %x" ,NSSCR0 ); -+ -+ SAVE(FFIER); -+ SAVE(FFLCR); -+ SAVE(FFMCR); -+ SAVE(FFSPR); -+ SAVE(FFISR); -+ FFLCR |= 0x80; -+ SAVE(FFDLL); -+ SAVE(FFDLH); -+ SAVE(FFFCR); -+ FFLCR &= 0xef; -+ -+ SAVE(STIER); -+ SAVE(STLCR); -+ SAVE(STMCR); -+ SAVE(STSPR); -+ SAVE(STISR); -+ STLCR |= 0x80; -+ SAVE(STDLL); -+ SAVE(STDLH); -+ STLCR &= 0xef; -+ -+ SAVE(BTIER); -+ SAVE(BTLCR); -+ SAVE(BTMCR); -+ SAVE(BTSPR); -+ SAVE(BTISR); -+ BTLCR |= 0x80; -+ SAVE(BTDLL); -+ SAVE(BTDLH); -+ BTLCR &= 0xef; -+ -+ /* save vital registers */ -+ SAVE(OSCR); -+ SAVE(OSMR0); -+ SAVE(OSMR1); -+ SAVE(OSMR2); -+ SAVE(OSMR3); -+ SAVE(OIER); - -- SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); - SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); - SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); - SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); -- SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); -- - SAVE(GAFR0_L); SAVE(GAFR0_U); - SAVE(GAFR1_L); SAVE(GAFR1_U); - SAVE(GAFR2_L); SAVE(GAFR2_U); - --#ifdef CONFIG_PXA27x -- SAVE(MDREFR); -- SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); -- SAVE(GAFR3_L); SAVE(GAFR3_U); -- SAVE(PWER); SAVE(PCFR); SAVE(PRER); -- SAVE(PFER); SAVE(PKWR); --#endif -+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 -----> -+ SAVE(LCCR0); SAVE(LCCR1); SAVE(LCCR2); SAVE(LCCR3); -+ SAVE(FDADR0); -+ SAVE(FDADR1); -+ LCSR = 0xffffffff; /* Clear LCD Status Register */ -+ -+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ -+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ -+ -+ SAVE(LDCMD0); -+ // <----- YoKu -+ -+// LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ -+// LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ -+ - - SAVE(ICMR); - ICMR = 0; - - SAVE(CKEN); -- SAVE(PSTR); -+ CKEN = 0; -+ -+ // Anup : For Wifi power saving mode 2 May 2006 -+ SAVE(NSSCR0);SAVE(NSSCR1);SAVE(NSSSR);SAVE(NSSITR);SAVE(NSSDR);SAVE(NSSTO); -+ SAVE(NSSPSP); -+ printk("\nMY favourite mode in life.......sleep.....\n"); -+ - - /* Note: wake up source are set up in each machine specific files */ - -+ /*Changes to keep the right sim selected */ -+ gpsr0 = GPLR0; -+ gpsr1 = GPLR1; -+ gpsr2 = GPLR2; -+ -+ /*Sim 1 selected */ -+ // YoKu GPIOs Changed -----> -+ if( (GPLR0 & GPIO_bit(21)) && !(GPLR0 & GPIO_bit(22)) ) // 62,63 -+ { -+ PGSR0 |= GPIO_bit(21) ; //62 -+ PGSR0 &= ~GPIO_bit(22) ; //63 -+ } -+ else if (!(GPLR0 & GPIO_bit(21)) && (GPLR0 & GPIO_bit(22)) ) // 62,63 -+ { -+ PGSR0 |= GPIO_bit(22) ; //63 -+ PGSR0 &= ~GPIO_bit(21) ; //62 -+ } /* sim 2*/ -+ // <----- YoKu -+ - /* clear GPIO transition detect bits */ - GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; --#ifdef CONFIG_PXA27x -- GEDR3 = GEDR3; --#endif - - /* Clear sleep reset status */ - RCSR = RCSR_SMR; - -+ /* set resume return address */ -+ PSPR = virt_to_phys(pxa_cpu_resume); -+ - /* before sleeping, calculate and save a checksum */ - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) - checksum += sleep_save[i]; - sleep_save[SLEEP_SAVE_CKSUM] = checksum; - -- /* *** go zzz *** */ -- pxa_cpu_pm_enter(state); -+ PGSR0 |= GPIO_bit(15); //sidd for wake from Sleep 15, YoKu Comented ?? GPIO15 was ChipSelect -+ PGSR2 |= GPIO_bit(80); //sidd for GSM Engine 69, YoKu GPIO Changed Anup :commented -+ -+ PGSR1 &= ~GPIO_bit(33); //Tushar: BT Codec Power Down -+ -+ PGSR0 &= ~GPIO_bit(23); //Tushar: BGW200 Regulator OFF -+ -+// GPDR1 |= GPIO_bit(49); //Tushar: LCD Serial Data in changed to O/P -+ -+// PGSR1 &= ~GPIO_bit(48);//Tushar: LCD Serial Pins -+ -+// PGSR1 &= ~GPIO_bit(49); -+ -+// PGSR1 &= ~GPIO_bit(50); -+ -+// PGSR1 |= GPIO_bit(51); -+ -+// PGSR1 &= 0x03FFFFFF;//Tushar: 24apr LCD datalines -+// PGSR2 &= 0xFFFFFC00; -+ -+ PGSR0 &= ~GPIO_bit(24); //Tushar: Mux Control Signals -+ -+ PGSR0 &= ~GPIO_bit(25); -+ -+ PGSR0 &= ~GPIO_bit(26); -+ -+ PGSR0 &= ~GPIO_bit(27); -+ -+ // GPDR0 |= GPIO_bit(17); //Tushar: unused GPIOs 19apr -+ // GPCR0 |= GPIO_bit(17); -+ PGSR0 &= ~GPIO_bit(17); -+ -+// GPDR1 |= GPIO_bit(56); //Tushar: unused GPIOs 19apr -+ // GPCR1 |= GPIO_bit(56); -+ PGSR1 &= ~GPIO_bit(56); -+ -+// GPDR2 |= GPIO_bit(79);//Tushar: unused GPIOs 19apr -+// GPCR2 |= GPIO_bit(79); -+ PGSR2 &= ~GPIO_bit(79); -+ -+// GPDR1 |= 0x03F00000;//Tushar: unused GPIOs 19apr -+// GPCR1 |= 0x03F00000; -+ PGSR1 &= 0xFC0FFFFF; -+ -+ -+ GPDR0 |= GPIO_bit(19);//Tushar: SIM Present Inputs configured as outputs -+ GPDR0 |= GPIO_bit(20); -+ PGSR0 &= ~GPIO_bit(19); -+ PGSR0 &= ~GPIO_bit(20); -+ -+ -+//Tushar: 25apr FFRTS FFDTR & FFTXD -+ -+ PGSR1 |= GPIO_bit(39); -+ PGSR1 |= GPIO_bit(40); -+ PGSR1 |= GPIO_bit(41); -+/* -+ PGSR2 &= GPIO_bit(81); //Tushar: 24apr NSSP pins -+ PGSR2 &= GPIO_bit(82); -+ PGSR2 &= GPIO_bit(83); -+ -+ PGSR2 |= GPIO_bit(74); -+ PGSR2 |= GPIO_bit(75); -+ PGSR2 |= GPIO_bit(76); -+ PGSR2 |= GPIO_bit(77); -+*/ -+ if(pm_pwronoff) -+ { -+ /* We are here bcos of pressing of on off switch -+ We wake up now only on pwr switch */ -+ printk("Anup: Before sleeping \n"); -+ pm_pwronoff = 0; -+ PGSR0 &= ~GPIO_bit(23); //7 YoKu GPIO Changed -+ //PGSR2 &= ~GPIO_bit(64); //64 YoKu Commented in PWG500 64,7 was WifiReg, IN PWG600 it is 23 -+ -+ PGSR2 &= ~GPIO_bit(80); //69 YoKu GPIO Changed Anup : commnented -+ PWER = 0x0004; // YoKu Changed from 0x10 to 0x04 (i.e GPIO 4 -> 2) -+ PFER = 0x0004; -+ PRER = 0x0004; -+ -+// YoKu ----> -+// 11May2006 To reduce Power Off current from 7mA to 4mA -+ GPDR0 |= GPIO_bit(16); // BTReset o/p Low -+ PGSR0 &= ~GPIO_bit(16); -+ -+ GPDR1 |= GPIO_bit(33); // nMEC/nPDI o/p Low -+ PGSR1 &= ~GPIO_bit(33); -+ -+ GPDR1 |= GPIO_bit(45); // BTRTS o/p High -+ PGSR1 |= GPIO_bit(45); -+ -+ -+ GPDR1 |= GPIO_bit(43); // BTTXD o/p High -+ PGSR1 |= GPIO_bit(43); -+ -+ GPDR1 &= ~GPIO_bit(42); // BTRXD i/p -+ GPDR1 &= ~GPIO_bit(44); // BTCTS i/p -+// <---- YoKu -+ -+ PSPR = virt_to_phys(pxa_cpu_resume); // YoKu 29July05 to Resume from where u left, Original PSPR = 0 -+ } -+ -+ valbefore = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; // 62,63 YoKu GPIO Changed -+ -+ //printk("Anup: Before sleeping gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2); -+ //kirti pxa_cpu_suspend(); -+ //printk("KER_PM: Going to sleep zzzzzzzzz\n"); -+ -+// OSCC |= OSCC_OON; //Tushar: 18 apr. enable 32.768KHz Oscillator -+ -+// PCFR |= PCFR_OPDE; //Tushar: 18 apr. disable 3.6864MHz oscillator -+ -+ pxa_cpu_pm_enter(PM_SUSPEND_MEM); - - cpu_init(); - -+ //kirti~ -+ /**/ -+ //FFMCR |= UART_DTR ; -+ /**/ -+ - /* after sleeping, validate the checksum */ - checksum = 0; - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) -@@ -141,39 +464,63 @@ - checksum = 0; - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) - checksum += sleep_save[i]; -- - /* if invalid, display message and wait for a hardware reset */ -- if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) { -+ if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) -+ { - #ifdef CONFIG_ARCH_LUBBOCK - LUB_HEXLED = 0xbadbadc5; - #endif - while (1) -- pxa_cpu_pm_enter(state); -+ { -+ printk("\n\n\nKERN_PM: CRC Error!!! after wakeup\n\n\n"); // YoKu 25May06 -+ - } - -+ } -+ valafter = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed -+ pm_pedr = PEDR ; -+ - /* ensure not to come back here if it wasn't intended */ - PSPR = 0; - -+ /*printk("YoKu: gafr0_L=0x%08x gafr0_U=0x%08x\n",GAFR0_L,GAFR0_U); -+ printk(" gafr1_L= 0x%08x gafr1_U= 0x%08x\n",GAFR1_L,GAFR1_U); -+ printk(" gafr2_L= 0x%08x gafr2_U= 0x%08x\n",GAFR2_L,GAFR2_U); */ - /* restore registers */ -- RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); - RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); -+ RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); -+ RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); - RESTORE(GAFR0_L); RESTORE(GAFR0_U); - RESTORE(GAFR1_L); RESTORE(GAFR1_U); - RESTORE(GAFR2_L); RESTORE(GAFR2_U); -- RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); -- RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); -- RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); - --#ifdef CONFIG_PXA27x -- RESTORE(MDREFR); -- RESTORE_GPLEVEL(3); RESTORE(GPDR3); -- RESTORE(GAFR3_L); RESTORE(GAFR3_U); -- RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); -- RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); -- RESTORE(PFER); RESTORE(PKWR); --#endif - -- PSSR = PSSR_RDH | PSSR_PH; -+ // Anup : For Wifi power saving mode 2 May 2006 -+ RESTORE(NSSCR0);RESTORE(NSSCR1);RESTORE(NSSSR);RESTORE(NSSITR);RESTORE(NSSDR);RESTORE(NSSTO); -+ RESTORE(NSSPSP); -+ -+ // PSSR = PSSR_PH; -+ GPSR0 = gpsr0; -+ GPSR1 = gpsr1; -+ GPSR2 = gpsr2; -+ -+ // Anup : check values of these registers -+// printk("YoKu: gpsr0=0x%08x gpsr1=0x%08x gpsr2= 0x%08x\n",gpsr0,gpsr1,gpsr2); -+ //sidd -+ -+ GPCR0 |= ~gpsr0; -+ GPCR1 |= ~gpsr1; -+ GPCR2 |= ~gpsr2; -+ -+ -+ PSSR = ~PSSR_PH; -+ -+ RESTORE(OSMR0); -+ RESTORE(OSMR1); -+ RESTORE(OSMR2); -+ RESTORE(OSMR3); -+ RESTORE(OSCR); -+ RESTORE(OIER); - - RESTORE(CKEN); - -@@ -181,62 +528,181 @@ - ICCR = 1; - RESTORE(ICMR); - -- RESTORE(PSTR); -+ /* -+ * Temporary solution. This won't be necessary once -+ * we move pxa support into the serial driver. -+ * Restore the FF UART. -+ */ -+ RESTORE(BTMCR); -+ RESTORE(BTSPR); -+ RESTORE(BTLCR); -+ BTLCR |= 0x80; -+ RESTORE(BTDLH); -+ RESTORE(BTDLL); -+ RESTORE(BTLCR); -+ RESTORE(BTISR); -+ BTFCR = 0xc7; -+ RESTORE(BTIER); -+ -+ RESTORE(STMCR); -+ RESTORE(STSPR); -+ RESTORE(STLCR); -+ STLCR |= 0x80; -+ RESTORE(STDLH); -+ RESTORE(STDLL); -+ RESTORE(STLCR); -+ RESTORE(STISR); -+ STFCR = 0xc7; -+ RESTORE(STIER); -+ -+ RESTORE(FFMCR); -+ RESTORE(FFSPR); -+ RESTORE(FFLCR); -+ FFLCR |= 0x80; -+ RESTORE(FFDLH); -+ RESTORE(FFDLL); -+ RESTORE(FFLCR); -+ RESTORE(FFISR); -+ RESTORE(FFFCR); -+ FFFCR = 0xc7; -+ RESTORE(FFIER); -+ -+ // YoKu 23Feb06 Added To save LCD Registers, updated by kirti 24Feb06 -----> -+ RESTORE(LCCR3); RESTORE(LCCR2); RESTORE(LCCR1); -+ LCCR0=RESTORE(LCCR0) & ~LCCR0_ENB; -+ RESTORE(FDADR0); RESTORE(FDADR1); -+ LCCR0 |= LCCR0_ENB; -+ -+ // <----- YoKu - - /* restore current time */ -- rtc.tv_sec = RCNR; -- restore_time_delta(&delta, &rtc); -+ xtime.tv_sec = RCNR; -+ -+ valafter1 = GPLR0 & (GPIO_bit(21) | GPIO_bit(22)) ; //62,63 YoKu GPIO Changed -+ -+// SSCR0 &=0xFFFFFFFF; -+// printk("\nPM : val of SSCR0 = %x " , SSCR0); -+ -+ printk("KER_PM: Resumed at RCNR = %d RTSR= %x\n",RCNR,RTSR); -+ -+ printk("YoKu: pgsr0=0x%08x pgsr1=0x%08x pgsr2= 0x%08x\n",PGSR0,PGSR1,PGSR2); -+ -+ OSMR0 = 0; /* set initial match at 0 */ -+ OSSR = 0xf; /* clear status on all timers */ -+ OIER |= OIER_E0; /* enable match on timer 0 to cause interrupts */ -+ OSCR = 0; /* initialize free-running timer, force first match */ -+ -+ leds_event(led_start); -+ //kirti sti(); -+ // call i2c reset here----> -+ ICR = ICR_UR; -+ ISR = 0x7FF; //I2C_ISR_INIT; -+ ICR &= ~ICR_UR; -+ -+ ISAR = 0x32;//i2c->slave_addr; -+ -+ /* set control register values */ -+ ICR = (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE);//I2C_ICR_INIT; -+ -+ /* enable unit */ -+ ICR |= ICR_IUE; -+ udelay(100); -+ //<----- -+ -+ local_irq_enable(); - --#ifdef DEBUG -- printk(KERN_DEBUG "*** made it back from resume\n"); --#endif - - return 0; - } - --EXPORT_SYMBOL_GPL(pxa_pm_enter); -- - unsigned long sleep_phys_sp(void *sp) - { - return virt_to_phys(sp); - } - -+#ifdef CONFIG_SYSCTL - /* -- * Called after processes are frozen, but before we shut down devices. -+ * ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than -+ * linux/sysctl.h. -+ * -+ * This means our interface here won't survive long - it needs a new -+ * interface. Quick hack to get this working - use sysctl id 9999. - */ --int pxa_pm_prepare(suspend_state_t state) --{ -- extern int pxa_cpu_pm_prepare(suspend_state_t state); -+#warning ACPI broke the kernel, this interface needs to be fixed up. -+#define CTL_ACPI 9999 -+#define ACPI_S1_SLP_TYP 19 - -- return pxa_cpu_pm_prepare(state); -+/* -+ * Send us to sleep. -+ */ -+static int sysctl_pm_do_suspend(ctl_table *ctl, int write, struct file *filp, -+ void *buffer, size_t *lenp) -+{ -+ int retval=0; -+ unsigned i , clock ; -+ if (write) -+ { -+ char buf[16], *p; -+ unsigned int sleepsec; -+ int len,left = *lenp; -+ -+ len = left; -+ if (left > sizeof(buf)) -+ left = sizeof(buf); -+ if (!copy_from_user(buf, buffer, left)) -+ { -+ buf[sizeof(buf) - 1] = '\0'; -+ sleepsec = simple_strtoul(buf, &p, 0); -+ printk("\nSleeping %d Pwronoff=%x RCNR=%d\n",sleepsec,pm_pwronoff,RCNR); -+ printk("\nPWER %x PFER=%x PRER=%x\n",PWER,PFER,PRER); -+ RTAR = xtime.tv_sec + sleepsec; -+ printk("\nRTAR=%d \n",RTAR); -+ } -+ } -+ retval = pm_do_suspend(); -+ clock = get_memclk_frequency_10khz(); -+ return retval; - } -- --EXPORT_SYMBOL_GPL(pxa_pm_prepare); - - /* -- * Called after devices are re-setup, but before processes are thawed. -+static struct ctl_table pm_table[] = -+{ -+ {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend}, -+ {0} -+}; - */ --int pxa_pm_finish(suspend_state_t state) -+static struct ctl_table pm_table[] = - { -- return 0; -+ { -+ ctl_name: ACPI_S1_SLP_TYP, -+ procname: "suspend", -+ mode: 0600, -+ proc_handler: (proc_handler *)&sysctl_pm_do_suspend, -+ }, -+ { -+ ctl_name: 0 - } -+}; - --EXPORT_SYMBOL_GPL(pxa_pm_finish); -+static struct ctl_table pm_dir_table[] = -+{ -+ {CTL_ACPI, "pm", NULL, 0, 0555, pm_table}, -+ {0} -+}; - - /* -- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. -+ * Initialize power interface - */ --static struct pm_ops pxa_pm_ops = { -- .pm_disk_mode = PM_DISK_FIRMWARE, -- .prepare = pxa_pm_prepare, -- .enter = pxa_pm_enter, -- .finish = pxa_pm_finish, --}; -- --static int __init pxa_pm_init(void) -+static int __init pm_init(void) - { -- pm_set_ops(&pxa_pm_ops); -+ register_sysctl_table(pm_dir_table, 1); -+ /*Adi: Adjust for clock value to RTC -+ RTTR = RTC clk - 1*/ -+ RTTR = 32913; -+ - return 0; - } - --device_initcall(pxa_pm_init); -+__initcall(pm_init); -+ -+#endif -diff -NurbwB linux-2.6.17/arch/arm/mach-pxa/sleep.S linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S ---- linux-2.6.17/arch/arm/mach-pxa/sleep.S 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/arch/arm/mach-pxa/sleep.S 2006-09-11 13:07:05.000000000 -0700 -@@ -79,7 +79,7 @@ - ldr r5, [r4] - - @ enable SDRAM self-refresh mode -- orr r5, r5, #MDREFR_SLFRSH -+ orr r5, r5, #(MDREFR_SLFRSH | MDREFR_APD) - - #ifdef CONFIG_PXA27x - @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) -diff -NurbwB linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h ---- linux-2.6.17/include/asm-arm/arch-pxa/pxa-regs.h 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/include/asm-arm/arch-pxa/pxa-regs.h 2006-09-11 11:04:36.000000000 -0700 -@@ -1748,6 +1748,15 @@ - #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL)) - #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL)) - -+#define NSSCR0 __REG(0x41400000) /* SSP Port 1 Control Register 0 */ -+#define NSSCR1 __REG(0x41400004) /* SSP Port 1 Control Register 1 */ -+#define NSSSR __REG(0x41400008) /* SSP Port 1 Status Register */ -+#define NSSITR __REG(0x4140000C) /* SSP Port 1 Interrupt Test Register */ -+#define NSSDR __REG(0x41400010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */ -+#define NSSTO __REG(0x41400028) /* SSP Port 1 Time Out Register */ -+#define NSSPSP __REG(0x4140002C) /* SSP Port 1 Programmable Serial Port Register */ -+ -+ - /* - * MultiMediaCard (MMC) controller - */ -diff -NurbwB linux-2.6.17/kernel/power/main.c linux-2.6.17-patched/kernel/power/main.c ---- linux-2.6.17/kernel/power/main.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/kernel/power/main.c 2006-09-11 12:59:20.000000000 -0700 -@@ -66,10 +66,12 @@ - goto Enable_cpu; - } - -+ /* - if (freeze_processes()) { - error = -EAGAIN; - goto Thaw; - } -+ */ - - if ((free_pages = nr_free_pages()) < FREE_PAGE_NUMBER) { - pr_debug("PM: free some memory\n"); -@@ -110,12 +112,15 @@ - - local_irq_save(flags); - -+ /* - if ((error = device_power_down(PMSG_SUSPEND))) { - printk(KERN_ERR "Some devices failed to power down\n"); - goto Done; - } -+ */ -+ - error = pm_ops->enter(state); -- device_power_up(); -+ //device_power_up(); - Done: - local_irq_restore(flags); - return error; diff --git a/target/linux/pxa-2.6/patches/002-usb_gadget.patch b/target/linux/pxa-2.6/patches/002-usb_gadget.patch deleted file mode 100644 index b6766d9b3b..0000000000 --- a/target/linux/pxa-2.6/patches/002-usb_gadget.patch +++ /dev/null @@ -1,58 +0,0 @@ -diff -NurbwB linux-2.6.17/drivers/usb/gadget/pxa2xx_udc.c linux-2.6.17-patched/drivers/usb/gadget/pxa2xx_udc.c ---- linux-2.6.17/drivers/usb/gadget/pxa2xx_udc.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/usb/gadget/pxa2xx_udc.c 2006-09-11 13:02:39.000000000 -0700 -@@ -87,8 +87,8 @@ - static const char ep0name [] = "ep0"; - - --// #define USE_DMA --// #define USE_OUT_DMA -+#define USE_DMA -+#define USE_OUT_DMA - // #define DISABLE_TEST_MODE - - #ifdef CONFIG_ARCH_IXP4XX -@@ -1513,7 +1513,7 @@ - #endif - - /* try to clear these bits before we enable the udc */ -- udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); -+ udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RSTIR|UDCCR_RESIR); - - ep0_idle(dev); - dev->gadget.speed = USB_SPEED_UNKNOWN; -@@ -2043,6 +2043,9 @@ - struct pxa2xx_udc *dev = _dev; - int handled; - -+ -+ udc_set_mask_UDCCR( UDCCR_REM | UDCCR_SRM); -+ - dev->stats.irqs++; - HEX_DISPLAY(dev->stats.irqs); - do { -@@ -2137,6 +2139,8 @@ - /* we could also ask for 1 msec SOF (SIR) interrupts */ - - } while (handled); -+ -+ udc_clear_mask_UDCCR( UDCCR_SRM | UDCCR_REM); - return IRQ_HANDLED; - } - -@@ -2437,6 +2441,7 @@ - int retval, out_dma = 1; - u32 chiprev; - -+ local_irq_disable(); - /* insist on Intel/ARM/XScale */ - asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); - if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { -@@ -2553,6 +2558,7 @@ - #endif - } - #endif -+ local_irq_enable(); - create_proc_files(); - - return 0; diff --git a/target/linux/pxa-2.6/patches/004-skbuf_hack.patch b/target/linux/pxa-2.6/patches/004-skbuf_hack.patch deleted file mode 100644 index 434e3b98b1..0000000000 --- a/target/linux/pxa-2.6/patches/004-skbuf_hack.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- linux-2.6.17/include/linux/skbuff.h 2006-09-20 16:13:42.000000000 -0700 -+++ linux-2.6.17-patched/include/linux/skbuff.h 2006-09-20 16:14:29.000000000 -0700 -@@ -239,6 +239,7 @@ - } nh; - - union { -+ struct ethhdr *ethernet; - unsigned char *raw; - } mac; - diff --git a/target/linux/pxa-2.6/patches/005-mtd.patch b/target/linux/pxa-2.6/patches/005-mtd.patch deleted file mode 100644 index 6156b6a930..0000000000 --- a/target/linux/pxa-2.6/patches/005-mtd.patch +++ /dev/null @@ -1,111 +0,0 @@ -diff -Nurb linux-2.6.17/drivers/mtd/chips/cfi_cmdset_0001.c linux-2.6.17-patched/drivers/mtd/chips/cfi_cmdset_0001.c ---- linux-2.6.17/drivers/mtd/chips/cfi_cmdset_0001.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/mtd/chips/cfi_cmdset_0001.c 2006-09-25 11:27:06.000000000 -0700 -@@ -40,7 +40,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MANUFACTURER_INTEL 0x0089 - #define I82802AB 0x00ad -diff -Nurb linux-2.6.17/drivers/mtd/maps/lubbock-flash.c linux-2.6.17-patched/drivers/mtd/maps/lubbock-flash.c ---- linux-2.6.17/drivers/mtd/maps/lubbock-flash.c 2006-06-17 18:49:35.000000000 -0700 -+++ linux-2.6.17-patched/drivers/mtd/maps/lubbock-flash.c 2006-09-25 10:50:08.000000000 -0700 -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - - - #define ROM_ADDR 0x00000000 -@@ -48,24 +49,27 @@ - .inval_cache = lubbock_map_inval_cache, - } }; - --static struct mtd_partition lubbock_partitions[] = { -+static struct mtd_partition lubbock_partitions[] = -+{ - { -- .name = "Bootloader", -- .size = 0x00040000, -- .offset = 0, -- .mask_flags = MTD_WRITEABLE /* force read-only */ -- },{ -- .name = "Kernel", -- .size = 0x00100000, -- .offset = 0x00040000, -- },{ -- .name = "Filesystem", -- .size = MTDPART_SIZ_FULL, -- .offset = 0x00140000 -- } -+ .name = "root", -+ .offset = 0x00410000 -+ }, -+ { -+ .name = "kernel", -+ .size = 0x00150000, -+ .offset = 0x000B0000 -+ }, -+ { -+ .name = "bootloader", -+ .size = 0x000B0000, -+ .offset = 0x00000000 -+ }, - }; - -+ - static struct mtd_info *mymtds[2]; -+static struct mtd_info *merged_mtd; - static struct mtd_partition *parsed_parts[2]; - static int nr_parsed_parts[2]; - -@@ -83,8 +87,8 @@ - printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n", - flashboot?"Flash":"ROM", flashboot); - -- lubbock_maps[flashboot^1].name = "Lubbock Application Flash"; -- lubbock_maps[flashboot].name = "Lubbock Boot ROM"; -+ lubbock_maps[flashboot^1].name = "Flash-1"; -+ lubbock_maps[flashboot].name = "Flash-0"; - - for (i = 0; i < 2; i++) { - lubbock_maps[i].virt = ioremap(lubbock_maps[i].phys, WINDOW_SIZE); -@@ -125,25 +129,23 @@ - if (!mymtds[0] && !mymtds[1]) - return ret; - -- for (i = 0; i < 2; i++) { -- if (!mymtds[i]) { -- printk(KERN_WARNING "%s is absent. Skipping\n", lubbock_maps[i].name); -- } else if (nr_parsed_parts[i]) { -- add_mtd_partitions(mymtds[i], parsed_parts[i], nr_parsed_parts[i]); -- } else if (!i) { -- printk("Using static partitions on %s\n", lubbock_maps[i].name); -- add_mtd_partitions(mymtds[i], lubbock_partitions, ARRAY_SIZE(lubbock_partitions)); -- } else { -- printk("Registering %s as whole device\n", lubbock_maps[i].name); -- add_mtd_device(mymtds[i]); -- } -- } -+ if (mymtds[0] && mymtds[1]) { -+ merged_mtd = mtd_concat_create(mymtds, 2, "Concated Flash #1 and #2"); -+ if(merged_mtd) -+ add_mtd_partitions(merged_mtd, lubbock_partitions, ARRAY_SIZE(lubbock_partitions)); -+ else -+ printk("YoKu: Failed to concate\n"); - return 0; -+ } - } - - static void __exit cleanup_lubbock(void) - { - int i; -+ -+ del_mtd_partitions(merged_mtd); -+ map_destroy(merged_mtd); -+ - for (i = 0; i < 2; i++) { -- cgit v1.2.3