From 8ad0ba3a07b64c221db5a08523161a2cdda6194e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 10 Mar 2019 23:04:28 +0100 Subject: oxnas: move PCIe controller outside of simple-bus Move PCIe controller outside down to SoC level to avoid resource mapping problems. Also add more detailed error handling when mapping registers. Signed-off-by: Daniel Golle --- .../oxnas/files/drivers/pci/host/pcie-oxnas.c | 31 +++++++++++++++++----- 1 file changed, 24 insertions(+), 7 deletions(-) (limited to 'target/linux/oxnas/files') diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c index 68898c3beb..1dd13f9364 100644 --- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c +++ b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c @@ -420,34 +420,51 @@ oxnas_pcie_map_registers(struct platform_device *pdev, u32 pcie_ctrl_offset; ret = of_address_to_resource(np, 0, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse base register space\n"); return -EINVAL; + } + pcie->base = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->base) + if (!pcie->base) { + dev_err(&pdev->dev, "failed to map base register space\n"); return -ENOMEM; + } ret = of_address_to_resource(np, 1, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse inbound register space\n"); return -EINVAL; + } + pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->inbound) + if (!pcie->inbound) { + dev_err(&pdev->dev, "failed to map inbound register space\n"); return -ENOMEM; + } pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL); if (IS_ERR(pcie->phy)) { - if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) + if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) { + dev_err(&pdev->dev, "failed to probe phy\n"); return PTR_ERR(pcie->phy); + } + dev_warn(&pdev->dev, "phy not attached\n"); pcie->phy = NULL; } if (of_property_read_u32(np, "plxtech,pcie-outbound-offset", - &outbound_ctrl_offset)) + &outbound_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse outbound register offset\n"); return -EINVAL; + } pcie->outbound_offset = outbound_ctrl_offset; if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset", - &pcie_ctrl_offset)) + &pcie_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n"); return -EINVAL; + } pcie->pcie_ctrl_offset = pcie_ctrl_offset; return 0; -- cgit v1.2.3