From 72b58f2eb12ad4aa0c59481d0911dc5e39180eb5 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 26 Nov 2014 09:00:08 +0000 Subject: add new target 'oxnas' This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle SVN-Revision: 43388 --- target/linux/oxnas/files/drivers/clk/clk-oxnas.c | 262 +++++++++++++++++++++++ 1 file changed, 262 insertions(+) create mode 100644 target/linux/oxnas/files/drivers/clk/clk-oxnas.c (limited to 'target/linux/oxnas/files/drivers/clk') diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c new file mode 100644 index 0000000000..8d80c4f2b8 --- /dev/null +++ b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2010 Broadcom + * Copyright (C) 2012 Stephen Warren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ (1000 * 1000) + +static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long fin = parent_rate; + unsigned long pll0; + unsigned long fbdiv, refdiv, outdiv; + + pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0); + refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; + refdiv += 1; + outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; + outdiv += 1; + fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1); + + /* seems we will not be here when pll is bypassed, so ignore this + * case */ + + return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; +} + +static const char *pll_clk_parents[] = { + "oscillator", +}; + +static struct clk_ops plla_ops = { + .recalc_rate = plla_clk_recalc_rate, +}; + +static struct clk_init_data clk_plla_init = { + .name = "plla", + .ops = &plla_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_hw plla_hw = { + .init = &clk_plla_init, +}; + +static struct device_node *node_pllb; + +int pllb_clk_enable(struct clk_hw *hw) +{ + struct reset_control *rstc; + + rstc = of_reset_control_get(node_pllb, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + /* put PLL into bypass */ + oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); + wmb(); + udelay(10); + reset_control_assert(rstc); + udelay(10); + /* set PLL B control information */ + writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV), + SEC_CTRL_PLLB_CTRL0); + reset_control_deassert(rstc); + reset_control_put(rstc); + udelay(100); + oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); + + return 0; +} + +void pllb_clk_disable(struct clk_hw *hw) +{ + struct reset_control *rstc; + + /* put PLL into bypass */ + oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); + wmb(); + udelay(10); + + rstc = of_reset_control_get(node_pllb, NULL); + if (!IS_ERR(rstc)) + reset_control_assert(rstc); +} + +static struct clk_ops pllb_ops = { + .enable = pllb_clk_enable, + .disable = pllb_clk_disable, +}; + +static struct clk_init_data clk_pllb_init = { + .name = "pllb", + .ops = &pllb_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_hw pllb_hw = { + .init = &clk_pllb_init, +}; + +/* standard gate clock */ +struct clk_std { + struct clk_hw hw; + signed char bit; +}; + +#define NUM_STD_CLKS 17 +#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) + +static int std_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + + return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit); +} + +static int std_clk_enable(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + + writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL); + return 0; +} + +static void std_clk_disable(struct clk_hw *hw) +{ + struct clk_std *std = to_stdclk(hw); + + writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL); +} + +static struct clk_ops std_clk_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .is_enabled = std_clk_is_enabled, +}; + +static const char *std_clk_parents[] = { + "oscillator", +}; + +static const char *eth_parents[] = { + "gmacclk", +}; + +#define DECLARE_STD_CLKP(__clk, __bit, __parent) \ +static struct clk_init_data clk_##__clk##_init = { \ + .name = __stringify(__clk), \ + .ops = &std_clk_ops, \ + .parent_names = __parent, \ + .num_parents = ARRAY_SIZE(__parent), \ +}; \ + \ +static struct clk_std clk_##__clk = { \ + .bit = __bit, \ + .hw = { \ + .init = &clk_##__clk##_init, \ + }, \ +} + +#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \ + std_clk_parents) + +DECLARE_STD_CLK(leon, 0); +DECLARE_STD_CLK(dma_sgdma, 1); +DECLARE_STD_CLK(cipher, 2); +DECLARE_STD_CLK(sd, 3); +DECLARE_STD_CLK(sata, 4); +DECLARE_STD_CLK(audio, 5); +DECLARE_STD_CLK(usbmph, 6); +DECLARE_STD_CLKP(etha, 7, eth_parents); +DECLARE_STD_CLK(pciea, 8); +DECLARE_STD_CLK(static, 9); +DECLARE_STD_CLK(ethb, 10); +DECLARE_STD_CLK(pcieb, 11); +DECLARE_STD_CLK(ref600, 12); +DECLARE_STD_CLK(usbdev, 13); + +struct clk_hw *std_clk_hw_tbl[] = { + &clk_leon.hw, + &clk_dma_sgdma.hw, + &clk_cipher.hw, + &clk_sd.hw, + &clk_sata.hw, + &clk_audio.hw, + &clk_usbmph.hw, + &clk_etha.hw, + &clk_pciea.hw, + &clk_static.hw, + &clk_ethb.hw, + &clk_pcieb.hw, + &clk_ref600.hw, + &clk_usbdev.hw, +}; + +struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)]; + +static struct clk_onecell_data std_clk_data; + +void __init oxnas_init_stdclk(struct device_node *np) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) { + std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]); + BUG_ON(IS_ERR(std_clk_tbl[i])); + } + std_clk_data.clks = std_clk_tbl; + std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl); + of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data); +} +CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk); + +void __init oxnas_init_plla(struct device_node *np) +{ + struct clk *clk; + + clk = clk_register(NULL, &plla_hw); + BUG_ON(IS_ERR(clk)); + /* mark it as enabled */ + clk_prepare_enable(clk); + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); + +void __init oxnas_init_pllb(struct device_node *np) +{ + struct clk *clk; + + node_pllb = np; + + clk = clk_register(NULL, &pllb_hw); + BUG_ON(IS_ERR(clk)); + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); -- cgit v1.2.3