From 584d7c53bd2d286a71fe5e8244624f59c529cb26 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Wed, 7 Mar 2018 22:10:02 +0100 Subject: mvebu: new subtarget cortex A53 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces new subtarget for Marvell EBU Armada Cortex A53 processor based devices. The first device is Globalscale ESPRESSObin. Some hardware specs: SoC: Marvell Armada 3700LP (88F3720) dual core ARM Cortex A53 processor up to 1.2GHz RAM: 512MB, 1GB or 2GB DDR3 Storage: SATA interface µSD card slot with footprint for an optional 4GB EMMC 4MB SPI NOR flash for bootloader Ethernet: Topaz Networking Switch (88E6341) with 3x GbE ports Connectors: USB 3.0 USB 2.0 µUSB port connected to PL2303SA (USB to serial bridge controller) for UART access Expansion: 2x 46-pin GPIO headers for accessories and shields with I2C, GPIOs, PWM, UART, SPI, MMC, etc MiniPCIe slot Misc: Reset button, JTAG interface Currently booting only from µSD card is supported. The boards depending on date of dispatch can come with various U-Boot versions. For the newest version 2017.03-armada-17.10 no manual intervention should be needed to boot OpenWrt image. For the older ones it's necessary to modify default U-Boot environment: 1. Interrupt boot process to run U-Boot command line, 2. Run following commands: (for version 2017.03-armada-17.06 and 2017.03-armada-17.08) setenv bootcmd "load mmc 0:1 0x4d00000 boot.scr; source 0x4d00000" saveenv (for version 2015.01-armada-17.02 and 2015.01-armada-17.04) setenv bootargs "console=ttyMV0,115200 root=/dev/mmcblk0p2 rw rootwait" setenv bootcmd "ext4load mmc 0:1 ${fdt_addr} armada-3720-espressobin.dtb; ext4load mmc 0:1 ${kernel_addr} Image; booti ${kernel_addr} - ${fdt_addr}" saveenv 3. Poweroff, insert SD card with OpenWrt image, boot and enjoy. Signed-off-by: Tomasz Maciej Nowak --- ...rk-fix-PCIe-max-read-request-size-setting.patch | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch (limited to 'target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch') diff --git a/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch b/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch new file mode 100644 index 0000000000..eaf7b097b0 --- /dev/null +++ b/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch @@ -0,0 +1,63 @@ +From patchwork Thu Sep 28 12:58:37 2017 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,6/7] PCI: aardvark: fix PCIe max read request size setting +X-Patchwork-Submitter: Thomas Petazzoni +X-Patchwork-Id: 819591 +Message-Id: <20170928125838.11887-7-thomas.petazzoni@free-electrons.com> +To: Bjorn Helgaas , linux-pci@vger.kernel.org +Cc: Jason Cooper , Andrew Lunn , + Sebastian Hesselbarth , Gregory Clement + , + Nadav Haklai , Hanna Hawa , + Yehuda Yitschak , + linux-arm-kernel@lists.infradead.org, Antoine Tenart + , =?utf-8?q?Miqu=C3=A8l_Raynal?= + , Evan Wang , + Thomas Petazzoni +Date: Thu, 28 Sep 2017 14:58:37 +0200 +From: Thomas Petazzoni +List-Id: + +From: Evan Wang + +There is an obvious typo issue in the definition of the PCIe maximum +read request size: a bit shift is directly used as a value, while it +should be used to shift the correct value. + +This is part of fixing bug +https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was +reported as the user to be important to get a Intel 7260 mini-PCIe +WiFi card working. + +Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") +Signed-off-by: Evan Wang +Reviewed-by: Victor Gu +Reviewed-by: Nadav Haklai +[Thomas: tweak commit log.] +Signed-off-by: Thomas Petazzoni +--- + drivers/pci/host/pci-aardvark.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -33,6 +33,7 @@ + #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 + #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) + #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 ++#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 + #define PCIE_CORE_MPS_UNIT_BYTE 128 + #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 + #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) +@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct ad + (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << + PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | + PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | +- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; ++ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << ++ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); + advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); + + /* Program PCIe Control 2 to disable strict ordering */ -- cgit v1.2.3