From 1d94f72439034c112bfa4b694fc736123f4890a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Sun, 12 Dec 2021 08:19:37 +0100 Subject: kernel: bump 4.14 to 4.14.258 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rebased patches: * generic: 273-batman-adv-Convert-packet.h-to-uapi-header.patch * ipq806x: 0065-arm-override-compiler-flags.patch * mvebu: 513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch Removed patches: Fixed upstream: * ar71xx: 821-serial-core-add-support-for-boot-console-with-arbitr.patch * ath79: 921-serial-core-add-support-for-boot-console-with-arbitr.patch - in 4.14.256 via 9112e7ef87149b3d8093e7446d784117f6e18d69 * mvebu: 527-PCI-aardvark-allow-to-specify-link-capability.patch - in 4.14.257 via 62a3dc9b65a2b24800fc4267b8cf590fad135034 * mvebu: 524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch - should be hopefully fixed by the bunch of changes in .256 and .257 Run tested on ipq40xx/glinet-b1300 and mvebu/turris-omnia. Fixes: CVE-2021-3640 Signed-off-by: Petr Štetiar --- ...t-and-device-to-the-same-MAX-payload-size.patch | 138 --------------------- 1 file changed, 138 deletions(-) delete mode 100644 target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch (limited to 'target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch') diff --git a/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch deleted file mode 100644 index ab643b776f..0000000000 --- a/target/linux/mvebu/patches-4.14/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch +++ /dev/null @@ -1,138 +0,0 @@ -From patchwork Thu Sep 28 12:58:34 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2, - 3/7] PCI: aardvark: set host and device to the same MAX payload size -X-Patchwork-Submitter: Thomas Petazzoni -X-Patchwork-Id: 819587 -Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas , linux-pci@vger.kernel.org -Cc: Jason Cooper , Andrew Lunn , - Sebastian Hesselbarth , Gregory Clement - , - Nadav Haklai , Hanna Hawa , - Yehuda Yitschak , - linux-arm-kernel@lists.infradead.org, Antoine Tenart - , =?utf-8?q?Miqu=C3=A8l_Raynal?= - , Victor Gu , - Thomas Petazzoni -Date: Thu, 28 Sep 2017 14:58:34 +0200 -From: Thomas Petazzoni -List-Id: - -From: Victor Gu - -Since the Aardvark does not implement a PCIe root bus, the Linux PCIe -subsystem will not align the MAX payload size between the host and the -device. This patch ensures that the host and device have the same MAX -payload size, fixing a number of problems with various PCIe devices. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Victor Gu -Reviewed-by: Evan Wang -Reviewed-by: Nadav Haklai -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni ---- - drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 59 insertions(+), 1 deletion(-) - ---- a/drivers/pci/host/pci-aardvark.c -+++ b/drivers/pci/host/pci-aardvark.c -@@ -30,9 +30,11 @@ - #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 - #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 -+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 - #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 -+#define PCIE_CORE_MPS_UNIT_BYTE 128 - #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 - #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) - #define PCIE_CORE_LINK_TRAINING BIT(5) -@@ -300,7 +302,8 @@ static void advk_pcie_setup_hw(struct ad - - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | -- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | -+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << -+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); -@@ -968,6 +971,58 @@ out_release_res: - return err; - } - -+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data) -+{ -+ u8 *smpss = data; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ if (*smpss > dev->pcie_mpss) -+ *smpss = dev->pcie_mpss; -+ -+ return 0; -+} -+ -+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data) -+{ -+ int mps; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data; -+ pcie_set_mps(dev, mps); -+ -+ return 0; -+} -+ -+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie) -+{ -+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ; -+ u32 reg; -+ -+ /* Find the minimal supported MAX payload size */ -+ advk_pcie_find_smpss(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss); -+ -+ /* Configure RC MAX payload size */ -+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG); -+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD; -+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT; -+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); -+ -+ /* Configure device MAX payload size */ -+ advk_pcie_bus_configure_mps(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss); -+} -+ - static int advk_pcie_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -1042,6 +1097,9 @@ static int advk_pcie_probe(struct platfo - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - -+ /* Configure the MAX pay load size */ -+ advk_pcie_configure_mps(bus, pcie); -+ - pci_bus_add_devices(bus); - return 0; - } -- cgit v1.2.3