From 8ee595315d46d4975a883a2022a133612e2a02e1 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 2 May 2012 18:27:22 +0000 Subject: mpc83xx: add support for 3.3 SVN-Revision: 31553 --- .../linux/mpc83xx/patches-3.3/111-etsec27_war.patch | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 target/linux/mpc83xx/patches-3.3/111-etsec27_war.patch (limited to 'target/linux/mpc83xx/patches-3.3/111-etsec27_war.patch') diff --git a/target/linux/mpc83xx/patches-3.3/111-etsec27_war.patch b/target/linux/mpc83xx/patches-3.3/111-etsec27_war.patch new file mode 100644 index 0000000000..44686ab515 --- /dev/null +++ b/target/linux/mpc83xx/patches-3.3/111-etsec27_war.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ethernet/freescale/gianfar.c ++++ b/drivers/net/ethernet/freescale/gianfar.c +@@ -1005,7 +1005,16 @@ static int gfar_probe(struct platform_de + /* We need to delay at least 3 TX clocks */ + udelay(2); + +- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); ++ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) { ++ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); ++ } else { ++ /* ++ * Do not enable flow control on chips earlier than rev 1.1, ++ * because of the eTSEC27 erratum ++ */ ++ tempval = 0; ++ } ++ + gfar_write(®s->maccfg1, tempval); + + /* Initialize MACCFG2. */ -- cgit v1.2.3