From b00640bd062e3f496f349c05218dabf5cafcd8e2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 16 Oct 2022 19:35:50 +0100 Subject: mediatek: don't break auxadc without 32k clk Make the newly added 32k clock optional for the auxadc driver also used on pre-filogic platforms. Signed-off-by: Daniel Golle --- .../patches-5.15/501-auxadc-add-auxadc-32k-clk.patch | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'target/linux/mediatek') diff --git a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch index a49fbca4ee..5b98235ff4 100644 --- a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch +++ b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch @@ -8,14 +8,16 @@ struct mutex lock; const struct mtk_auxadc_compatible *dev_comp; }; -@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_ +@@ -222,6 +223,14 @@ static int __maybe_unused mt6577_auxadc_ return ret; } -+ ret = clk_prepare_enable(adc_dev->adc_32k_clk); -+ if (ret) { -+ pr_err("failed to enable auxadc clock\n"); -+ return ret; ++ if (!IS_ERR(adc_dev->adc_32k_clk)) { ++ ret = clk_prepare_enable(adc_dev->adc_32k_clk); ++ if (ret) { ++ pr_err("failed to enable auxadc clock\n"); ++ return ret; ++ } + } + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, -- cgit v1.2.3