From 0419f7deadf08c59a24f3db5991c0f704aa2241f Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 28 Sep 2022 19:37:43 +0100 Subject: mediatek: add support t-phy settings from efuse on MT7986 Import patches from mtk-openwrt-feeds (MTK SDK) to support reading t-phy settings affecting PCIe as well as USB2 and USB3 from efuse. Signed-off-by: Daniel Golle --- .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 32 ++- ...hy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch | 225 +++++++++++++++++++++ ...-tphy-add-auto-load-valid-check-mechanism.patch | 149 ++++++++++++++ 3 files changed, 405 insertions(+), 1 deletion(-) create mode 100644 target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch create mode 100644 target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch (limited to 'target/linux/mediatek') diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 648e043bc1..e135fee35a 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -341,7 +341,7 @@ pcie_phy: t-phy@11c00000 { compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; + "mediatek,generic-tphy-v4"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -352,6 +352,24 @@ clocks = <&clk40m>; clock-names = "ref"; #phy-cells = <1>; + auto_load_valid; + auto_load_valid_ln1; + nvmem-cells = <&pcie_intr_ln0>, + <&pcie_rx_imp_ln0>, + <&pcie_tx_imp_ln0>, + <&pcie_auto_load_valid_ln0>, + <&pcie_intr_ln1>, + <&pcie_rx_imp_ln1>, + <&pcie_tx_imp_ln1>, + <&pcie_auto_load_valid_ln1>; + nvmem-cell-names = "intr", + "rx_imp", + "tx_imp", + "auto_load_valid", + "intr_ln1", + "rx_imp_ln1", + "tx_imp_ln1", + "auto_load_valid_ln1"; }; }; @@ -462,6 +480,9 @@ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; clock-names = "ref", "da_ref"; #phy-cells = <1>; + auto_load_valid; + nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>; + nvmem-cell-names = "intr", "auto_load_valid"; }; u3port0: usb-phy@11e10700 { @@ -469,6 +490,12 @@ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; clock-names = "ref"; #phy-cells = <1>; + auto_load_valid; + nvmem-cells = <&comb_intr_p0>, + <&comb_rx_imp_p0>, + <&comb_tx_imp_p0>, + <&comb_auto_load_valid>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid"; }; u2port1: usb-phy@11e11000 { @@ -477,6 +504,9 @@ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; clock-names = "ref", "da_ref"; #phy-cells = <1>; + auto_load_valid; + nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>; + nvmem-cell-names = "intr", "auto_load_valid"; }; }; diff --git a/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch new file mode 100644 index 0000000000..4c2fd18b3b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch @@ -0,0 +1,225 @@ +From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 16:50:47 +0800 +Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support + +Add PCIe 2 lane efuse support in tphy driver. + +Signed-off-by: Jie Yang +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ + 1 file changed, 140 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -44,6 +44,15 @@ + #define SSUSB_SIFSLV_V2_U3PHYD 0x200 + #define SSUSB_SIFSLV_V2_U3PHYA 0x400 + ++/* version V4 sub-banks offset base address */ ++/* pcie phy banks */ ++#define SSUSB_SIFSLV_V4_SPLLC 0x000 ++#define SSUSB_SIFSLV_V4_CHIP 0x100 ++#define SSUSB_SIFSLV_V4_U3PHYD 0x900 ++#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 ++ ++#define SSUSB_LN1_OFFSET 0x10000 ++ + #define U3P_MISC_REG1 0x04 + #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) + +@@ -320,6 +329,7 @@ enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, + MTK_PHY_V3, ++ MTK_PHY_V4, + }; + + struct mtk_phy_pdata { +@@ -369,6 +379,9 @@ struct mtk_phy_instance { + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ u32 efuse_intr_ln1; ++ u32 efuse_tx_imp_ln1; ++ u32 efuse_rx_imp_ln1; + int eye_src; + int eye_vrt; + int eye_term; +@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk + } + } + ++static void phy_v4_banks_init(struct mtk_tphy *tphy, ++ struct mtk_phy_instance *instance) ++{ ++ struct u2phy_banks *u2_banks = &instance->u2_banks; ++ struct u3phy_banks *u3_banks = &instance->u3_banks; ++ ++ switch (instance->type) { ++ case PHY_TYPE_USB2: ++ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; ++ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; ++ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; ++ break; ++ case PHY_TYPE_USB3: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; ++ break; ++ case PHY_TYPE_PCIE: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; ++ break; ++ default: ++ dev_err(tphy->dev, "incompatible PHY type\n"); ++ return; ++ } ++} ++ + static void phy_parse_property(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + { +@@ -1143,6 +1186,40 @@ static int phy_efuse_get(struct mtk_tphy + + dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", + instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); ++ ++ if (tphy->pdata->version != MTK_PHY_V4) ++ break; ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ /* no efuse, ignore it */ ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) { ++ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); ++ instance->efuse_sw_en = 0; ++ break; ++ } ++ ++ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", ++ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, ++ instance->efuse_tx_imp_ln1); + break; + default: + dev_err(dev, "no sw efuse for type %d\n", instance->type); +@@ -1174,6 +1251,31 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); ++ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp, ++ instance->efuse_rx_imp, instance->efuse_intr); ++ ++ break; + case PHY_TYPE_PCIE: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; +@@ -1195,6 +1297,34 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) ++ break; ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); ++ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp_ln1, ++ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); + break; + default: + dev_warn(dev, "no sw efuse for type %d\n", instance->type); +@@ -1334,6 +1464,9 @@ static struct phy *mtk_phy_xlate(struct + case MTK_PHY_V3: + phy_v2_banks_init(tphy, instance); + break; ++ case MTK_PHY_V4: ++ phy_v4_banks_init(tphy, instance); ++ break; + default: + dev_err(dev, "phy version is not supported\n"); + return ERR_PTR(-EINVAL); +@@ -1374,6 +1507,12 @@ static const struct mtk_phy_pdata tphy_v + .version = MTK_PHY_V3, + }; + ++static const struct mtk_phy_pdata tphy_v4_pdata = { ++ .avoid_rx_sen_degradation = false, ++ .sw_efuse_supported = true, ++ .version = MTK_PHY_V4, ++}; ++ + static const struct mtk_phy_pdata mt8173_pdata = { + .avoid_rx_sen_degradation = true, + .version = MTK_PHY_V1, +@@ -1393,6 +1532,7 @@ static const struct of_device_id mtk_tph + { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, + { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, ++ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, + { }, + }; + MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch new file mode 100644 index 0000000000..67580f1e11 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch @@ -0,0 +1,149 @@ +From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 19:03:34 +0800 +Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism + support + +add auto-load-valid check mechanism support + +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- + 1 file changed, 64 insertions(+), 3 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -376,9 +376,13 @@ struct mtk_phy_instance { + u32 type_sw_reg; + u32 type_sw_index; + u32 efuse_sw_en; ++ bool efuse_alv_en; ++ u32 efuse_autoloadvalid; + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ bool efuse_alv_ln1_en; ++ u32 efuse_ln1_autoloadvalid; + u32 efuse_intr_ln1; + u32 efuse_tx_imp_ln1; + u32 efuse_rx_imp_ln1; +@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy + { + struct device *dev = &instance->phy->dev; + int ret = 0; ++ bool alv = false; + + /* tphy v1 doesn't support sw efuse, skip it */ + if (!tphy->pdata->sw_efuse_supported) { +@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u2 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); +@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy + + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u3 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); +@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy + if (tphy->pdata->version != MTK_PHY_V4) + break; + ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); ++ if (alv) { ++ instance->efuse_alv_ln1_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", ++ &instance->efuse_ln1_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "pcie auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_ln1_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); +@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u2_banks->misc + U3P_MISC_REG1); + tmp |= MR1_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u2_banks->misc + U3P_MISC_REG1); +@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy + + break; + case PHY_TYPE_PCIE: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); +- if (!instance->efuse_intr_ln1 && +- !instance->efuse_rx_imp_ln1 && +- !instance->efuse_tx_imp_ln1) ++ ++ if ((!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) || ++ (instance->efuse_alv_ln1_en && ++ instance->efuse_ln1_autoloadvalid == 1)) + break; + + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); 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