From 196f3d586f11d96ba4ab60068cfb12420bcd20fd Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Thu, 4 Mar 2021 13:37:13 -0700 Subject: kernel-5.4: bump to 5.4.102 and refresh patches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 5.4.102 backported a lot of stuff that our WireGuard backport already did, in addition to other patches we had, so those patches were removed from that part of the series. In the process other patches were refreshed or reworked to account for upstream changes. This commit involved `update_kernel.sh -v -u 5.4`. Cc: John Audia Cc: David Bauer Cc: Petr Štetiar Signed-off-by: Jason A. Donenfeld --- .../1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch') diff --git a/target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index c24126284b..20a67676e3 100644 --- a/target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -803,6 +803,8 @@ +@@ -805,6 +805,8 @@ reg = <0 0x1a143000 0 0x1000>; reg-names = "port0"; mediatek,pcie-cfg = <&pciecfg>; @@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau #address-cells = <3>; #size-cells = <2>; interrupts = ; -@@ -820,6 +822,7 @@ +@@ -822,6 +824,7 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; status = "disabled"; @@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau slot0: pcie@0,0 { reg = <0x0000 0 0 0 0>; -@@ -846,6 +849,8 @@ +@@ -848,6 +851,8 @@ reg = <0 0x1a145000 0 0x1000>; reg-names = "port1"; mediatek,pcie-cfg = <&pciecfg>; @@ -36,7 +36,7 @@ Signed-off-by: Felix Fietkau #address-cells = <3>; #size-cells = <2>; interrupts = ; -@@ -864,6 +869,7 @@ +@@ -866,6 +871,7 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; status = "disabled"; @@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau slot1: pcie@1,0 { reg = <0x0800 0 0 0 0>; -@@ -923,6 +929,11 @@ +@@ -925,6 +931,11 @@ }; }; -- cgit v1.2.3