From 25d9df670b850a4e3702e084ff249baa1670ae3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mark-MC=20Lee=20=28=E6=9D=8E=E6=98=8E=E6=98=8C=29?= Date: Mon, 10 Feb 2020 09:33:15 +0100 Subject: mediatek: add v5.4 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Mark-MC Lee (李明昌) --- .../patches-5.4/0005-dts-mt7622-add-gsw.patch | 257 +++++++++++++++++++++ 1 file changed, 257 insertions(+) create mode 100755 target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch (limited to 'target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch') diff --git a/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch b/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch new file mode 100755 index 0000000000..26c17f2245 --- /dev/null +++ b/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch @@ -0,0 +1,257 @@ +diff -urN a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2019-12-02 14:33:30.126586402 +0800 ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts 2019-12-02 14:35:02.304005081 +0800 +@@ -53,6 +53,13 @@ + }; + }; + ++ gsw: gsw@0 { ++ compatible = "mediatek,mt753x"; ++ mediatek,ethsys = <ðsys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -146,6 +153,36 @@ + }; + }; + ++&gsw { ++ mediatek,mdio = <&mdio>; ++ mediatek,portmap = "wllll"; ++ mediatek,mdio_master_pinmux = <0>; ++ reset-gpios = <&pio 54 0>; ++ interrupt-parent = <&pio>; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ ++ port5: port@5 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <5>; ++ phy-mode = "rgmii"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ port6: port@6 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <6>; ++ phy-mode = "sgmii"; ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-01-12 19:21:53.000000000 +0800 ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-01-15 15:36:50.987901563 +0800 +@@ -1,7 +1,6 @@ + /* +- * Copyright (c) 2017 MediaTek Inc. +- * Author: Ming Huang +- * Sean Wang ++ * Copyright (c) 2018 MediaTek Inc. ++ * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ +@@ -14,8 +13,8 @@ + #include "mt6380.dtsi" + + / { +- model = "MediaTek MT7622 RFB1 board"; +- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; ++ model = "MT7622_MT7531 RFB"; ++ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; + + aliases { + serial0 = &uart0; +@@ -23,7 +22,7 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; ++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { +@@ -40,23 +39,45 @@ + + gpio-keys { + compatible = "gpio-keys"; +- poll-interval = <100>; + + factory { + label = "factory"; + linux,code = ; +- gpios = <&pio 0 0>; ++ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "wps"; + linux,code = ; +- gpios = <&pio 102 0>; ++ gpios = <&pio 102 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ gsw: gsw@0 { ++ compatible = "mediatek,mt753x"; ++ mediatek,ethsys = <ðsys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green { ++ label = "bpi-r64:pio:green"; ++ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ red { ++ label = "bpi-r64:pio:red"; ++ gpios = <&pio 88 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; + }; + }; + + memory { +- reg = <0 0x40000000 0 0x20000000>; ++ reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { +@@ -101,27 +122,67 @@ + }; + + ð { +- pinctrl-names = "default"; +- pinctrl-0 = <ð_pins>; + status = "okay"; ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "2500base-x"; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ pause; ++ }; ++ }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; +- phy-handle = <&phy5>; ++ phy-mode = "rgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; + }; + +- mdio-bus { ++ mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; +- +- phy5: ethernet-phy@5 { +- reg = <5>; +- phy-mode = "sgmii"; +- }; + }; + }; + ++&gsw { ++ mediatek,mdio = <&mdio>; ++ mediatek,portmap = "llllw"; ++ mediatek,mdio_master_pinmux = <0>; ++ reset-gpios = <&pio 54 0>; ++ interrupt-parent = <&pio>; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ ++ port5: port@5 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <5>; ++ phy-mode = "rgmii"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ port6: port@6 { ++ compatible = "mediatek,mt753x-port"; ++ reg = <6>; ++ phy-mode = "sgmii"; ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ }; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +@@ -185,15 +246,28 @@ + + &pcie { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_pins>; ++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; + }; + + &pio { ++ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and ++ * SATA functions. i.e. output-high: PCIe, output-low: SATA ++ */ ++ asm_sel { ++ gpio-hog; ++ gpios = <90 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++ + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { +@@ -460,11 +534,11 @@ + }; + + &sata { +- status = "okay"; ++ status = "disable"; + }; + + &sata_phy { +- status = "okay"; ++ status = "disable"; + }; + + &spi0 { -- cgit v1.2.3