From 53f5d59fa17049d94a3992d1067ded1fa90f61f8 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 16 Feb 2017 09:53:03 +0100 Subject: mediatek: bump to v4.9 Signed-off-by: John Crispin --- .../patches-4.4/0017-clk-add-hifsys-reset.patch | 47 ---------------------- 1 file changed, 47 deletions(-) delete mode 100644 target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch (limited to 'target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch') diff --git a/target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch b/target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch deleted file mode 100644 index d7d151cedb..0000000000 --- a/target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f7121d2b19ddad33a09408a2c5923bfd95da8533 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 6 Jan 2016 20:06:49 +0100 -Subject: [PATCH 017/102] clk: add hifsys reset - -Hi, - -small patch to add hifsys reset bits. Maybe you could add it to the next -version of your patch series. i have teste scpsys and clk on mt7623 today -and it works well. - -thanks, - John - -Signed-off-by: John Crispin ---- - drivers/clk/mediatek/clk-mt2701.c | 2 ++ - include/dt-bindings/reset-controller/mt2701-resets.h | 9 +++++++++ - 2 files changed, 11 insertions(+) - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -+ -+ mtk_register_reset_controller(node, 1, 0x34); - } - CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init); - ---- a/include/dt-bindings/reset-controller/mt2701-resets.h -+++ b/include/dt-bindings/reset-controller/mt2701-resets.h -@@ -71,4 +71,13 @@ - #define MT2701_TOPRGU_CONN_MCU_RST 12 - #define MT2701_TOPRGU_BDP_DISP_RST 13 - -+/* HIFSYS resets */ -+#define MT2701_HIFSYS_UHOST0_RST 3 -+#define MT2701_HIFSYS_UHOST1_RST 4 -+#define MT2701_HIFSYS_UPHY0_RST 21 -+#define MT2701_HIFSYS_UPHY1_RST 22 -+#define MT2701_HIFSYS_PCIE0_RST 24 -+#define MT2701_HIFSYS_PCIE1_RST 25 -+#define MT2701_HIFSYS_PCIE2_RST 26 -+ - #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ -- cgit v1.2.3