From 278512665094888d3c007fdd74e090496d6c811d Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Fri, 9 Oct 2020 21:53:35 +0200 Subject: kernel: remove support for kernel 4.19 We use 5.4 on all targets by default, and 4.19 has never been released in a stable version. There is no reason to keep it. Signed-off-by: Adrian Schmutzler --- .../0003-mt7531-gsw-internal_phy_calibration.patch | 1261 -------------------- 1 file changed, 1261 deletions(-) delete mode 100644 target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch (limited to 'target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch') diff --git a/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch b/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch deleted file mode 100644 index db22cc2189..0000000000 --- a/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch +++ /dev/null @@ -1,1261 +0,0 @@ ---- a/drivers/net/phy/mtk/mt753x/Makefile -+++ b/drivers/net/phy/mtk/mt753x/Makefile -@@ -8,4 +8,4 @@ mt753x-$(CONFIG_SWCONFIG) += mt753x_swco - - mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \ - mt753x_common.o mt753x_vlan.o \ -- mt753x_nl.o -+ mt753x_nl.o mt753x_phy.o ---- a/drivers/net/phy/mtk/mt753x/mt7531.c -+++ b/drivers/net/phy/mtk/mt753x/mt7531.c -@@ -585,6 +585,27 @@ static void mt7531_core_pll_setup(struct - - static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw) - { -+ u32 i, val; -+ int ret; -+ -+ dev_info(gsw->dev,">>>>>>>>>>>>>>>>>>>>>>>>>>>>> START CALIBRATION:\n"); -+ -+ /* gphy value from sw path */ -+ val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); -+ val |= GBE_EFUSE_SETTING; -+ gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); -+ -+ for (i = 0; i < 5; i++) { -+ dev_info(gsw->dev, "-------- gephy-calbration (port:%d) --------\n", -+ i); -+ ret = mt753x_phy_calibration(gsw, i); -+ -+ /* set Auto-negotiation with giga extension. */ -+ gsw->mii_write(gsw, i, 0, 0x1340); -+ if (ret) -+ return ret; -+ } -+ - return 0; - } - ---- a/drivers/net/phy/mtk/mt753x/mt753x.h -+++ b/drivers/net/phy/mtk/mt753x/mt753x.h -@@ -129,6 +129,8 @@ void mt753x_mmd_ind_write(struct gsw_mt7 - void mt753x_irq_worker(struct work_struct *work); - void mt753x_irq_enable(struct gsw_mt753x *gsw); - -+int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr); -+ - /* MDIO Indirect Access Registers */ - #define MII_MMD_ACC_CTL_REG 0x0d - #define MMD_CMD_S 14 ---- /dev/null -+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c -@@ -0,0 +1,1061 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Common part for MediaTek MT753x gigabit switch -+ * -+ * Copyright (C) 2018 MediaTek Inc. All Rights Reserved. -+ * -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+ -+#include "mt753x.h" -+#include "mt753x_regs.h" -+#include "mt753x_phy.h" -+ -+u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr) -+{ -+ u32 phy_val; -+ phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr); -+ -+ //printk("switch phy cl45 r %d 0x%x 0x%x = %x\n",port_num, dev_addr, reg_addr, phy_val); -+ //switch_phy_read_cl45(port_num, dev_addr, reg_addr, &phy_val); -+ return phy_val; -+} -+ -+void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data) -+{ -+ u32 phy_val; -+ gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data); -+ phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr); -+ //printk("switch phy cl45 w %d 0x%x 0x%x 0x%x --> read back 0x%x\n",port_num, dev_addr, reg_addr, write_data, phy_val); -+ //switch_phy_write_cl45(port_num, dev_addr, reg_addr, write_data); -+} -+ -+void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){ -+ gsw->mii_write(gsw, port_num, reg_addr, write_data); -+} -+ -+u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){ -+ return gsw->mii_read(gsw, port_num, reg_addr); -+} -+ -+const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = { -+ 127, 127, 127, 127, 127, 127, 127, 127, -+ 127, 127, 127, 127, 127, 123, 122, 117, -+ 115, 112, 103, 100, 98, 87, 85, 83, -+ 81, 72, 70, 68, 66, 64, 55, 53, -+ 52, 50, 49, 48, 38, 36, 35, 34, -+ 33, 32, 22, 21, 20, 19, 18, 17, -+ 16, 7, 6, 5, 4, 3, 2, 1, -+ 0, 0, 0, 0, 0, 0, 0, 0 -+}; -+ -+const u8 MT753x_TX_OFFSET_TBL[64] = { -+ 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, -+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, -+ 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, -+ 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0, -+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, -+ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, -+ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, -+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f -+}; -+ -+u8 ge_cal_flag; -+ -+u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512 -+{ -+ u8 all_ana_cal_status; -+ u32 cnt, tmp_1e_17c; -+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017c, 0x0001); // da_calin_flag pull high -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); -+ //printk("delay = %d\n", delay); -+ -+ cnt = 10000; -+ do { -+ udelay(delay); -+ cnt--; -+ all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1; -+ -+ } while ((all_ana_cal_status == 0) && (cnt != 0)); -+ -+ -+ if(all_ana_cal_status == 1) { -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); -+ return all_ana_cal_status; -+ } else { -+ tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c); -+ if ((tmp_1e_17c & 0x1) != 1) { -+ pr_info("FIRST MDC/MDIO write error\n"); -+ pr_info("FIRST 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c)); -+ -+ } -+ printk("re-K again\n"); -+ -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); -+ cnt = 10000; -+ do { -+ udelay(delay); -+ cnt--; -+ tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c); -+ if ((tmp_1e_17c & 0x1) != 1) { -+ pr_info("SECOND MDC/MDIO write error\n"); -+ pr_info("SECOND 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c)); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); -+ } -+ } while ((cnt != 0) && (tmp_1e_17c == 0)); -+ -+ cnt = 10000; -+ do { -+ udelay(delay); -+ cnt--; -+ all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1; -+ -+ } while ((all_ana_cal_status == 0) && (cnt != 0)); -+ -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); -+ } -+ -+ if(all_ana_cal_status == 0){ -+ pr_info("!!!!!!!!!!!! dev1Eh_reg17b ERROR\n"); -+ } -+ -+ return all_ana_cal_status; -+} -+ -+ -+ -+ -+int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) -+{ -+ u8 rg_zcal_ctrl, all_ana_cal_status; -+ u16 ad_cal_comp_out_init; -+ u16 dev1e_e0_ana_cal_r5; -+ int calibration_polarity; -+ u8 cnt = 0; -+ u16 dev1e_17a_tmp, dev1e_e0_tmp; -+ -+ /* *** Iext/Rext Cal start ************ */ -+ all_ana_cal_status = ANACAL_INIT; -+ /* analog calibration enable, Rext calibration enable */ -+ /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */ -+ /* 1e_dc[0]:rg_txvos_calen */ -+ /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */ -+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110) -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110); -+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0); -+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000); -+ //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10); -+ -+ rg_zcal_ctrl = 0x20;/* start with 0 dB */ -+ dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); // get default value -+ /* 1e_e0[5:0]:rg_zcal_ctrl */ -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl); -+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */ -+ -+ if (all_ana_cal_status == 0) { -+ all_ana_cal_status = ANACAL_ERROR; -+ printk(" GE Rext AnaCal ERROR init! \r\n"); -+ return -1; -+ } -+ /* 1e_17a[8]:ad_cal_comp_out */ -+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1; -+ if (ad_cal_comp_out_init == 1) -+ calibration_polarity = -1; -+ else /* ad_cal_comp_out_init == 0 */ -+ calibration_polarity = 1; -+ cnt = 0; -+ while (all_ana_cal_status < ANACAL_ERROR) { -+ cnt++; -+ rg_zcal_ctrl += calibration_polarity; -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl)); -+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */ -+ dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); -+ if (all_ana_cal_status == 0) { -+ all_ana_cal_status = ANACAL_ERROR; -+ printk(" GE Rext AnaCal ERROR 2! \r\n"); -+ return -1; -+ } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) { -+ all_ana_cal_status = ANACAL_FINISH; -+ //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl); -+ } else { -+ dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); -+ dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); -+ if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) { -+ all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */ -+ printk(" GE Rext AnaCal Saturation! \r\n"); -+ rg_zcal_ctrl = 0x20; /* 0 dB */ -+ } -+ } -+ } -+ -+ if (all_ana_cal_status == ANACAL_ERROR) { -+ rg_zcal_ctrl = 0x20; /* 0 dB */ -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); -+ } else if(all_ana_cal_status == ANACAL_FINISH){ -+ //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl)); -+ printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0)); -+ /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */ -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3)); -+ printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115)); -+ printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl); -+ ge_cal_flag = 1; -+ } else { -+ printk("GE Rxet cal something wrong2\n"); -+ } -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); -+} -+ -+//----------------------------------------------------------------- -+int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) -+{ -+ u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair; -+ u16 ad_cal_comp_out_init; -+ u16 dev1e_e0_ana_cal_r5; -+ int calibration_polarity; -+ u8 cnt = 0; -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // 1e_dc[0]:rg_txvos_calen -+ -+ for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) { -+ rg_zcal_ctrl = 0x20; // start with 0 dB -+ dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f)); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); // 1e_e0[5:0]:rg_zcal_ctrl -+ if(calibration_pair == ANACAL_PAIR_A) -+ { -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); -+ //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); -+ -+ } -+ else if(calibration_pair == ANACAL_PAIR_B) -+ { -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000); // 1e_dc[12]:rg_zcalen_b -+ //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); -+ -+ } -+ else if(calibration_pair == ANACAL_PAIR_C) -+ { -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100); // 1e_dc[8]:rg_zcalen_c -+ //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); -+ -+ } -+ else // if(calibration_pair == ANACAL_PAIR_D) -+ { -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010); // 1e_dc[4]:rg_zcalen_d -+ //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); -+ -+ } -+ -+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec -+ if(all_ana_cal_status == 0) -+ { -+ all_ana_cal_status = ANACAL_ERROR; -+ printk( "GE R50 AnaCal ERROR init! \r\n"); -+ return -1; -+ } -+ -+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out -+ if(ad_cal_comp_out_init == 1) -+ calibration_polarity = -1; -+ else -+ calibration_polarity = 1; -+ -+ cnt = 0; -+ while(all_ana_cal_status < ANACAL_ERROR) -+ { -+ cnt ++; -+ rg_zcal_ctrl += calibration_polarity; -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); -+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec -+ -+ if(all_ana_cal_status == 0) -+ { -+ all_ana_cal_status = ANACAL_ERROR; -+ printk( " GE R50 AnaCal ERROR 2! \r\n"); -+ return -1; -+ } -+ else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) -+ { -+ all_ana_cal_status = ANACAL_FINISH; -+ } -+ else { -+ if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00)) -+ { -+ all_ana_cal_status = ANACAL_SATURATION; // need to FT -+ printk( " GE R50 AnaCal Saturation! \r\n"); -+ } -+ } -+ } -+ -+ if(all_ana_cal_status == ANACAL_ERROR) { -+ rg_zcal_ctrl = 0x20; // 0 dB -+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); -+ } -+ else { -+ rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9]; // wait Mog zcal/r50 mapping table -+ printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80)); -+ } -+ -+ if(calibration_pair == ANACAL_PAIR_A) { -+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00); -+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174); -+ //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_174[15:8] -+ //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ } -+ else if(calibration_pair == ANACAL_PAIR_B) { -+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f); -+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174); -+ //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_174[7:0] -+ //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ } -+ else if(calibration_pair == ANACAL_PAIR_C) { -+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00); -+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_175[15:8] -+ //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ } else {// if(calibration_pair == ANACAL_PAIR_D) -+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f); -+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_175[7:0] -+ //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ } -+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl)); -+ } -+ -+ printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); -+} -+ -+int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) -+{ -+ u8 all_ana_cal_status, calibration_pair; -+ u16 ad_cal_comp_out_init; -+ int calibration_polarity, tx_offset_temp; -+ u8 tx_offset_reg_shift, tabl_idx, i; -+ u8 cnt = 0; -+ u16 tx_offset_reg, reg_temp, cal_temp; -+ //switch_phy_write(phyaddr, R0, 0x2100);//harry tmp -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a -+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000); // 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e -+ for(i = 0; i <= 4; i++) -+ tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000); -+ for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) -+ { -+ tabl_idx = 31; -+ tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx]; -+ -+ if(calibration_pair == ANACAL_PAIR_A) { -+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:rg_txg_calen_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V)); // 1e_17d:dac_in0_a -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V)); // 1e_181:dac_in1_a -+ //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181)); -+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00)); -+ tx_offset_reg_shift = 8; // 1e_172[13:8] -+ tx_offset_reg = 0x0172; -+ -+ //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out -+ if(ad_cal_comp_out_init == 1) -+ calibration_polarity = 1; -+ else -+ calibration_polarity = -1; -+ -+ cnt = 0; -+ //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]); -+ while(all_ana_cal_status < ANACAL_ERROR) { -+ -+ cnt ++; -+ tabl_idx += calibration_polarity; -+ //tx_offset_temp += calibration_polarity; -+ //cal_temp = tx_offset_temp; -+ cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx]; -+ //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<>8)&0x1) != ad_cal_comp_out_init) { -+ all_ana_cal_status = ANACAL_FINISH; -+ } else { -+ if((tabl_idx == 0)||(tabl_idx == 0x3f)) { -+ all_ana_cal_status = ANACAL_SATURATION; // need to FT -+ printk( " GE Tx offset AnaCal Saturation! \r\n"); -+ } -+ } -+ } -+ -+ if(all_ana_cal_status == ANACAL_ERROR) { -+ tx_offset_temp = TX_AMP_OFFSET_0MV; -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out -+ if(ad_cal_comp_out_init == 1) -+ calibration_polarity = -1; -+ else -+ calibration_polarity = 1; -+ -+ cnt =0; -+ while(all_ana_cal_status < ANACAL_ERROR) { -+ cnt ++; -+ tx_amp_temp += calibration_polarity; -+ //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<>8)&0x1) != ad_cal_comp_out_init) { -+ //printk("TX AMP ANACAL_FINISH\n"); -+ all_ana_cal_status = ANACAL_FINISH; -+ if (phyaddr == 0) { -+ if (calibration_pair == ANACAL_PAIR_A) -+ tx_amp_temp = tx_amp_temp - 2; -+ else if(calibration_pair == ANACAL_PAIR_B) -+ tx_amp_temp = tx_amp_temp - 1; -+ else if(calibration_pair == ANACAL_PAIR_C) -+ tx_amp_temp = tx_amp_temp - 2; -+ else if(calibration_pair == ANACAL_PAIR_D) -+ tx_amp_temp = tx_amp_temp - 1; -+ } else if (phyaddr == 1) { -+ if (calibration_pair == ANACAL_PAIR_A) -+ tx_amp_temp = tx_amp_temp - 1; -+ else if(calibration_pair == ANACAL_PAIR_B) -+ tx_amp_temp = tx_amp_temp ; -+ else if(calibration_pair == ANACAL_PAIR_C) -+ tx_amp_temp = tx_amp_temp - 1; -+ else if(calibration_pair == ANACAL_PAIR_D) -+ tx_amp_temp = tx_amp_temp - 1; -+ } else if (phyaddr == 2) { -+ if (calibration_pair == ANACAL_PAIR_A) -+ tx_amp_temp = tx_amp_temp; -+ else if(calibration_pair == ANACAL_PAIR_B) -+ tx_amp_temp = tx_amp_temp - 1; -+ else if(calibration_pair == ANACAL_PAIR_C) -+ tx_amp_temp = tx_amp_temp; -+ else if(calibration_pair == ANACAL_PAIR_D) -+ tx_amp_temp = tx_amp_temp - 1; -+ } else if (phyaddr == 3) { -+ tx_amp_temp = tx_amp_temp; -+ } else if (phyaddr == 4) { -+ if (calibration_pair == ANACAL_PAIR_A) -+ tx_amp_temp = tx_amp_temp; -+ else if(calibration_pair == ANACAL_PAIR_B) -+ tx_amp_temp = tx_amp_temp - 1; -+ else if(calibration_pair == ANACAL_PAIR_C) -+ tx_amp_temp = tx_amp_temp; -+ else if(calibration_pair == ANACAL_PAIR_D) -+ tx_amp_temp = tx_amp_temp; -+ } -+ reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<> 10); -+ reg_tmp -= 8; -+ reg_backup = 0x0000; -+ reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0)); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); -+ //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); -+ reg_tmp = ((reg_backup & 0x3f) >> 0); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f)); -+ reg_backup |= (reg_tmp << 0); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); -+ //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup); -+ } -+ else if(calibration_pair == ANACAL_PAIR_B){ -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); -+ reg_tmp = ((reg_backup & 0x3f00) >> 8); -+ reg_tmp -= 8; -+ reg_backup = 0x0000; -+ reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0)); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); -+ //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); -+ reg_tmp = ((reg_backup & 0x3f) >> 0); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f)); -+ reg_backup |= (reg_tmp << 0); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); -+ //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup); -+ } -+ else if(calibration_pair == ANACAL_PAIR_C){ -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); -+ reg_tmp = ((reg_backup & 0x3f00) >> 8); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f00)); -+ reg_backup |= (reg_tmp << 8); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); -+ //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); -+ reg_tmp = ((reg_backup & 0x3f) >> 0); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f)); -+ reg_backup |= (reg_tmp << 0); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); -+ //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup); -+ } -+ else if(calibration_pair == ANACAL_PAIR_D){ -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); -+ reg_tmp = ((reg_backup & 0x3f00) >> 8); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f00)); -+ reg_backup |= (reg_tmp << 8); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); -+ //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); -+ reg_tmp = ((reg_backup & 0x3f) >> 0); -+ reg_tmp -= 8; -+ reg_backup = (reg_backup & (~0x3f)); -+ reg_backup |= (reg_tmp << 0); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup); -+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); -+ //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup); -+ } -+ -+ if (calibration_pair == ANACAL_PAIR_A){ -+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); -+ //printk("1e.012 = 0x%x\n", debug_tmp); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); -+ //printk("1e.016 = 0x%x\n", debug_tmp); -+ } -+ -+ else if(calibration_pair == ANACAL_PAIR_B){ -+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); -+ //printk("1e.017 = 0x%x\n", debug_tmp); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); -+ //printk("1e.018 = 0x%x\n", debug_tmp); -+ } -+ else if(calibration_pair == ANACAL_PAIR_C){ -+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); -+ //printk("1e.019 = 0x%x\n", debug_tmp); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); -+ //printk("1e.020 = 0x%x\n", debug_tmp); -+ } -+ else if(calibration_pair == ANACAL_PAIR_D){ -+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); -+ //printk("1e.021 = 0x%x\n", debug_tmp); -+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); -+ //printk("1e.022 = 0x%x\n", debug_tmp); -+ } -+ -+ -+ printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); -+ -+ } else { -+ if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) { -+ all_ana_cal_status = ANACAL_SATURATION; // need to FT -+ printk( " GE Tx amp AnaCal Saturation! \r\n"); -+ } -+ } -+ } -+ -+ if(all_ana_cal_status == ANACAL_ERROR) { -+ tx_amp_temp = 0x20; -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<4) -+ pr_info("pairA RX_DC_OFFSET error"); -+} -+ -+void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr) -+{ -+ u32 reg_tmp; -+ u8 reg_val; -+ -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("before pairB output = %x\n", reg_tmp); -+ udelay(40); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143); -+ udelay(40); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("after pairB output = %x\n", reg_tmp); -+ if ((reg_tmp & 0x80) != 0) -+ reg_tmp = (~reg_tmp) + 1; -+ if ((reg_tmp & 0xff) >4) -+ pr_info("pairB RX_DC_OFFSET error"); -+} -+ -+void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr) -+{ -+ u32 reg_tmp; -+ u8 reg_val; -+ -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("before pairC output = %x\n", reg_tmp); -+ udelay(40); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144); -+ udelay(40); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("after pairC output = %x\n", reg_tmp); -+ if ((reg_tmp & 0x80) != 0) -+ reg_tmp = (~reg_tmp) + 1; -+ if ((reg_tmp & 0xff) >4) -+ pr_info("pairC RX_DC_OFFSET error"); -+} -+ -+void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr) -+{ -+ u32 reg_tmp; -+ u8 reg_val; -+ -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("before pairD output = %x\n", reg_tmp); -+ udelay(40); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145); -+ udelay(40); -+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); -+ reg_tmp = reg_tmp & 0xff; -+ pr_info("after pairD output = %x\n", reg_tmp); -+ if ((reg_tmp & 0x80) != 0) -+ reg_tmp = (~reg_tmp) + 1; -+ if ((reg_tmp & 0xff) >4) -+ pr_info("pairD RX_DC_OFFSET error"); -+} -+ -+ -+int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){ -+ -+ int ret; -+ -+ phy_calibration(gsw, phyaddr); -+ -+ /*eye pic*/ -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0, 0x187); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x1, 0x1c9); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x2, 0x1c6); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3, 0x182); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x4, 0x208); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x5, 0x205); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x6, 0x384); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x7, 0x3cb); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x8, 0x3c4); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x9, 0x30a); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xa, 0x00b); -+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xb, 0x002); -+ -+ rx_dc_offset(gsw, phyaddr); -+ check_rx_dc_offset_pair_a(gsw, phyaddr); -+ check_rx_dc_offset_pair_b(gsw, phyaddr); -+ check_rx_dc_offset_pair_c(gsw, phyaddr); -+ check_rx_dc_offset_pair_d(gsw, phyaddr); -+ -+ return ret; -+} ---- /dev/null -+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h -@@ -0,0 +1,145 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Register definitions for MediaTek MT753x Gigabit switches -+ * -+ * Copyright (C) 2018 MediaTek Inc. All Rights Reserved. -+ * -+ * Author: Weijie Gao -+ */ -+ -+#ifndef _MT753X_PHY_H_ -+#define _MT753X_PHY_H_ -+ -+#include -+ -+/*phy calibration use*/ -+#define DEV_1E 0x1E -+/*global device 0x1f, always set P0*/ -+#define DEV_1F 0x1F -+ -+ -+/************IEXT/REXT CAL***************/ -+/* bits range: for example BITS(16,23) = 0xFF0000*/ -+#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) -+#define ANACAL_INIT 0x01 -+#define ANACAL_ERROR 0xFD -+#define ANACAL_SATURATION 0xFE -+#define ANACAL_FINISH 0xFF -+#define ANACAL_PAIR_A 0 -+#define ANACAL_PAIR_B 1 -+#define ANACAL_PAIR_C 2 -+#define ANACAL_PAIR_D 3 -+#define DAC_IN_0V 0x00 -+#define DAC_IN_2V 0xf0 -+#define TX_AMP_OFFSET_0MV 0x20 -+#define TX_AMP_OFFSET_VALID_BITS 6 -+ -+#define R0 0 -+#define PHY0 0 -+#define PHY1 1 -+#define PHY2 2 -+#define PHY3 3 -+#define PHY4 4 -+#define ANA_TEST_MODE BITS(8, 15) -+#define TST_TCLK_SEL BITs(6, 7) -+#define ANA_TEST_VGA_RG 0x100 -+ -+#define FORCE_MDI_CROSS_OVER BITS(3, 4) -+#define T10_TEST_CTL_RG 0x145 -+#define RG_185 0x185 -+#define RG_TX_SLEW BIT(0) -+#define ANA_CAL_0 0xdb -+#define RG_CAL_CKINV BIT(12) -+#define RG_ANA_CALEN BIT(8) -+#define RG_REXT_CALEN BIT(4) -+#define RG_ZCALEN_A BIT(0) -+#define ANA_CAL_1 0xdc -+#define RG_ZCALEN_B BIT(12) -+#define RG_ZCALEN_C BIT(8) -+#define RG_ZCALEN_D BIT(4) -+#define RG_TXVOS_CALEN BIT(0) -+#define ANA_CAL_6 0xe1 -+#define RG_CAL_REFSEL BIT(4) -+#define RG_CAL_COMP_PWD BIT(0) -+#define ANA_CAL_5 0xe0 -+#define RG_REXT_TRIM BITs(8, 13) -+#define RG_ZCAL_CTRL BITs(0, 5) -+#define RG_17A 0x17a -+#define AD_CAL_COMP_OUT BIT(8) -+#define RG_17B 0x17b -+#define AD_CAL_CLK bit(0) -+#define RG_17C 0x17c -+#define DA_CALIN_FLAG bit(0) -+/************R50 CAL****************************/ -+#define RG_174 0x174 -+#define RG_R50OHM_RSEL_TX_A_EN BIT[15] -+#define CR_R50OHM_RSEL_TX_A BITS[8:14] -+#define RG_R50OHM_RSEL_TX_B_EN BIT[7] -+#define CR_R50OHM_RSEL_TX_B BITS[6:0] -+#define RG_175 0x175 -+#define RG_R50OHM_RSEL_TX_C_EN BITS[15] -+#define CR_R50OHM_RSEL_TX_C BITS[8:14] -+#define RG_R50OHM_RSEL_TX_D_EN BIT[7] -+#define CR_R50OHM_RSEL_TX_D BITS[0:6] -+/**********TX offset Calibration***************************/ -+#define RG_95 0x96 -+#define BYPASS_TX_OFFSET_CAL BIT(15) -+#define RG_3E 0x3e -+#define BYPASS_PD_TXVLD_A BIT(15) -+#define BYPASS_PD_TXVLD_B BIT(14) -+#define BYPASS_PD_TXVLD_C BIT(13) -+#define BYPASS_PD_TXVLD_D BIT(12) -+#define BYPASS_PD_TX_10M BIT(11) -+#define POWER_DOWN_TXVLD_A BIT(7) -+#define POWER_DOWN_TXVLD_B BIT(6) -+#define POWER_DOWN_TXVLD_C BIT(5) -+#define POWER_DOWN_TXVLD_D BIT(4) -+#define POWER_DOWN_TX_10M BIT(3) -+#define RG_DD 0xdd -+#define RG_TXG_CALEN_A BIT(12) -+#define RG_TXG_CALEN_B BIT(8) -+#define RG_TXG_CALEN_C BIT(4) -+#define RG_TXG_CALEN_D BIT(0) -+#define RG_17D 0x17D -+#define FORCE_DASN_DAC_IN0_A BIT(15) -+#define DASN_DAC_IN0_A BITS(0, 9) -+#define RG_17E 0x17E -+#define FORCE_DASN_DAC_IN0_B BIT(15) -+#define DASN_DAC_IN0_B BITS(0, 9) -+#define RG_17F 0x17F -+ -+#define FORCE_DASN_DAC_IN0_C BIT(15) -+#define DASN_DAC_IN0_C BITS(0, 9) -+#define RG_180 0x180 -+#define FORCE_DASN_DAC_IN0_D BIT(15) -+#define DASN_DAC_IN0_D BITS(0, 9) -+ -+#define RG_181 0x181 -+#define FORCE_DASN_DAC_IN1_A BIT(15) -+#define DASN_DAC_IN1_A BITS(0, 9) -+#define RG_182 0x182 -+#define FORCE_DASN_DAC_IN1_B BIT(15) -+#define DASN_DAC_IN1_B BITS(0, 9) -+#define RG_183 0x183 -+#define FORCE_DASN_DAC_IN1_C BIT15] -+#define DASN_DAC_IN1_C BITS(0, 9) -+#define RG_184 0x184 -+#define FORCE_DASN_DAC_IN1_D BIT(15) -+#define DASN_DAC_IN1_D BITS(0, 9) -+#define RG_172 0x172 -+#define CR_TX_AMP_OFFSET_A BITS(8, 13) -+#define CR_TX_AMP_OFFSET_B BITS(0, 5) -+#define RG_173 0x173 -+#define CR_TX_AMP_OFFSET_C BITS(8, 13) -+#define CR_TX_AMP_OFFSET_D BITS(0, 5) -+/**********TX Amp Calibration ***************************/ -+#define RG_12 0x12 -+#define DA_TX_I2MPB_A_GBE BITS(10, 15) -+#define RG_17 0x17 -+#define DA_TX_I2MPB_B_GBE BITS(8, 13) -+#define RG_19 0x19 -+#define DA_TX_I2MPB_C_GBE BITS(8, 13) -+#define RG_21 0x21 -+#define DA_TX_I2MPB_D_GBE BITS(8, 13) -+ -+#endif /* _MT753X_REGS_H_ */ -- cgit v1.2.3