From 050da2107a7eb2a571a8a3d0cee21cc6a44b72b8 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 7 May 2018 12:07:32 +0200 Subject: mediatek: backport upstream mediatek patches Signed-off-by: John Crispin --- ...s-mt7622-add-pinctrl-related-device-nodes.patch | 259 +++++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch (limited to 'target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch') diff --git a/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch b/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch new file mode 100644 index 0000000000..9858790450 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch @@ -0,0 +1,259 @@ +From 927c736a1a169713cd59140db5e82f8ed11dad60 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 29 Dec 2017 11:06:52 +0800 +Subject: [PATCH 212/224] arm64: dts: mt7622: add pinctrl related device nodes + +add pinctrl device nodes and rfb1 board, additionally include all pin +groups possible being used on rfb1 board and available gpio keys. + +Signed-off-by: Sean Wang +Cc: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 + + 2 files changed, 207 insertions(+) + +diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +index c08309df2cc7..fc8ef78a0a34 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -7,6 +7,8 @@ + */ + + /dts-v1/; ++#include ++ + #include "mt7622.dtsi" + + / { +@@ -17,11 +19,209 @@ + bootargs = "console=ttyS0,115200n1"; + }; + ++ gpio-keys { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ factory { ++ label = "factory"; ++ linux,code = ; ++ gpios = <&pio 0 0>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 102 0>; ++ }; ++ }; ++ + memory { + reg = <0 0x40000000 0 0x3F000000>; + }; + }; + ++&pio { ++ /* eMMC is shared pin with parallel NAND */ ++ emmc_pins_default: emmc-pins-default { ++ mux { ++ function = "emmc", "emmc_rst"; ++ groups = "emmc"; ++ }; ++ }; ++ ++ emmc_pins_uhs: emmc-pins-uhs { ++ mux { ++ function = "emmc"; ++ groups = "emmc"; ++ }; ++ }; ++ ++ eth_pins: eth-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio", "rgmii_via_gmac2"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2s1_pins: i2s1-pins { ++ mux { ++ function = "i2s"; ++ groups = "i2s_out_bclk_ws_mclk", ++ "i2s1_in_data", ++ "i2s1_out_data"; ++ }; ++ }; ++ ++ irrx_pins: irrx-pins { ++ mux { ++ function = "ir"; ++ groups = "ir_1_rx"; ++ }; ++ }; ++ ++ irtx_pins: irtx-pins { ++ mux { ++ function = "ir"; ++ groups = "ir_1_tx"; ++ }; ++ }; ++ ++ /* Parallel nand is shared pin with eMMC */ ++ parallel_nand_pins: parallel-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "par_nand"; ++ }; ++ }; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie0_pad_perst", ++ "pcie0_1_waken", ++ "pcie0_1_clkreq"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie1_pad_perst", ++ "pcie1_0_waken", ++ "pcie1_0_clkreq"; ++ }; ++ }; ++ ++ pmic_bus_pins: pmic-bus-pins { ++ mux { ++ function = "pmic"; ++ groups = "pmic_bus"; ++ }; ++ }; ++ ++ pwm7_pins: pwm1-2-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm_ch7_2"; ++ }; ++ }; ++ ++ wled_pins: wled-pins { ++ mux { ++ function = "led"; ++ groups = "wled"; ++ }; ++ }; ++ ++ sd0_pins_default: sd0-pins-default { ++ mux { ++ function = "sd"; ++ groups = "sd_0"; ++ }; ++ }; ++ ++ sd0_pins_uhs: sd0-pins-uhs { ++ mux { ++ function = "sd"; ++ groups = "sd_0"; ++ }; ++ }; ++ ++ /* Serial NAND is shared pin with SPI-NOR */ ++ serial_nand_pins: serial-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spic0_pins: spic0-pins { ++ mux { ++ function = "spi"; ++ groups = "spic0_0"; ++ }; ++ }; ++ ++ spic1_pins: spic1-pins { ++ mux { ++ function = "spi"; ++ groups = "spic1_0"; ++ }; ++ }; ++ ++ /* SPI-NOR is shared pin with serial NAND */ ++ spi_nor_pins: spi-nor-pins { ++ mux { ++ function = "flash"; ++ groups = "spi_nor"; ++ }; ++ }; ++ ++ /* serial NAND is shared pin with SPI-NOR */ ++ serial_nand_pins: serial-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0_0_tx_rx" ; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_1_tx_rx" ; ++ }; ++ }; ++ ++ watchdog_pins: watchdog-pins { ++ mux { ++ function = "watchdog"; ++ groups = "watchdog"; ++ }; ++ }; ++}; ++ + &uart0 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +index 81207e652d59..8211bf72ccaa 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -147,6 +147,13 @@ + #clock-cells = <1>; + }; + ++ pio: pinctrl@10211000 { ++ compatible = "mediatek,mt7622-pinctrl"; ++ reg = <0 0x10211000 0 0x1000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; +-- +2.11.0 + -- cgit v1.2.3