From cddd4591404fb4c53dc0b3c0b15b942cdbed4356 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 10 Apr 2020 10:47:05 +0800 Subject: layerscape: add patches-5.4 Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu --- ...andle-RCPM-errata-A-008646-on-SoC-LS1021A.patch | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 target/linux/layerscape/patches-5.4/813-pm-0005-soc-fsl-handle-RCPM-errata-A-008646-on-SoC-LS1021A.patch (limited to 'target/linux/layerscape/patches-5.4/813-pm-0005-soc-fsl-handle-RCPM-errata-A-008646-on-SoC-LS1021A.patch') diff --git a/target/linux/layerscape/patches-5.4/813-pm-0005-soc-fsl-handle-RCPM-errata-A-008646-on-SoC-LS1021A.patch b/target/linux/layerscape/patches-5.4/813-pm-0005-soc-fsl-handle-RCPM-errata-A-008646-on-SoC-LS1021A.patch new file mode 100644 index 0000000000..faf5627b9d --- /dev/null +++ b/target/linux/layerscape/patches-5.4/813-pm-0005-soc-fsl-handle-RCPM-errata-A-008646-on-SoC-LS1021A.patch @@ -0,0 +1,100 @@ +From 12ae7ff3ecb4527ebe30ec6feb29ebb0ec4cd0a7 Mon Sep 17 00:00:00 2001 +From: Biwen Li +Date: Sat, 14 Sep 2019 12:37:49 +0800 +Subject: [PATCH] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A + +Description: + - Reading configuration register RCPM_IPPDEXPCR1 + always return zero + +Workaround: + - Save register RCPM_IPPDEXPCR1's value to + register SCFG_SPARECR8.(uboot's psci also + need reading value from the register SCFG_SPARECR8 + to set register RCPM_IPPDEXPCR1) + +Impact: + - FlexTimer module will cannot wakeup system in + deep sleep on SoC LS1021A + +Reviewed-by: Ran Wang +Signed-off-by: Biwen Li +--- + drivers/soc/fsl/rcpm.c | 47 +++++++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 45 insertions(+), 2 deletions(-) + +--- a/drivers/soc/fsl/rcpm.c ++++ b/drivers/soc/fsl/rcpm.c +@@ -6,13 +6,16 @@ + // + // Author: Ran Wang + ++#include + #include ++#include ++#include + #include +-#include + #include ++#include ++#include + #include + #include +-#include + + #define RCPM_WAKEUP_CELL_MAX_SIZE 7 + +@@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device + struct device_node *np = dev->of_node; + u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1]; + u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0}; ++ struct regmap *scfg_addr_regmap = NULL; ++ u32 reg_offset[RCPM_WAKEUP_CELL_MAX_SIZE + 1]; ++ u32 reg_value = 0; + + rcpm = dev_get_drvdata(dev); + if (!rcpm) +@@ -90,6 +96,43 @@ static int rcpm_pm_prepare(struct device + tmp |= ioread32be(address); + iowrite32be(tmp, address); + } ++ /* ++ * Workaround of errata A-008646 on SoC LS1021A: ++ * There is a bug of register ippdexpcr1. ++ * Reading configuration register RCPM_IPPDEXPCR1 ++ * always return zero. So save ippdexpcr1's value ++ * to register SCFG_SPARECR8.And the value of ++ * ippdexpcr1 will be read from SCFG_SPARECR8. ++ */ ++ if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr")) { ++ if (dev_of_node(dev)) { ++ scfg_addr_regmap = syscon_regmap_lookup_by_phandle(np, ++ "fsl,ippdexpcr1-alt-addr"); ++ } else if (is_acpi_node(dev->fwnode)) { ++ dev_err(dev, "not support acpi for rcpm\n"); ++ continue; ++ } ++ ++ if (scfg_addr_regmap && (i == 1)) { ++ if (device_property_read_u32_array(dev, ++ "fsl,ippdexpcr1-alt-addr", ++ reg_offset, ++ 1 + sizeof(u64)/sizeof(u32))) { ++ scfg_addr_regmap = NULL; ++ continue; ++ } ++ /* Read value from register SCFG_SPARECR8 */ ++ regmap_read(scfg_addr_regmap, ++ (u32)(((u64)(reg_offset[1] << (sizeof(u32) * 8) | ++ reg_offset[2])) & 0xffffffff), ++ ®_value); ++ /* Write value to register SCFG_SPARECR8 */ ++ regmap_write(scfg_addr_regmap, ++ (u32)(((u64)(reg_offset[1] << (sizeof(u32) * 8) | ++ reg_offset[2])) & 0xffffffff), ++ tmp | reg_value); ++ } ++ } + } + + return 0; -- cgit v1.2.3