From cddd4591404fb4c53dc0b3c0b15b942cdbed4356 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 10 Apr 2020 10:47:05 +0800 Subject: layerscape: add patches-5.4 Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu --- ...l-Add-8-bit-and-16-bit-CSR-register-acces.patch | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch (limited to 'target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch') diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch b/target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch new file mode 100644 index 0000000000..ee8c519520 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch @@ -0,0 +1,47 @@ +From 7e92994ec22c9d337f6012ac913e7958012ad52e Mon Sep 17 00:00:00 2001 +From: Hou Zhiqiang +Date: Tue, 25 Jun 2019 09:09:28 +0000 +Subject: [PATCH] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors + +There are some 8-bit and 16-bit registers in PCIe configuration +space, so add these accessors accordingly. + +Signed-off-by: Hou Zhiqiang +Reviewed-by: Minghuan Lian +Reviewed-by: Subrahmanya Lingappa +--- + drivers/pci/controller/mobiveil/pcie-mobiveil.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h ++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h +@@ -182,9 +182,29 @@ static inline u32 csr_readl(struct mobiv + return csr_read(pcie, off, 0x4); + } + ++static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) ++{ ++ return csr_read(pcie, off, 0x2); ++} ++ ++static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) ++{ ++ return csr_read(pcie, off, 0x1); ++} ++ + static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) + { + csr_write(pcie, val, off, 0x4); + } + ++static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) ++{ ++ csr_write(pcie, val, off, 0x2); ++} ++ ++static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) ++{ ++ csr_write(pcie, val, off, 0x1); ++} ++ + #endif /* _PCIE_MOBIVEIL_H */ -- cgit v1.2.3