From cddd4591404fb4c53dc0b3c0b15b942cdbed4356 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 10 Apr 2020 10:47:05 +0800 Subject: layerscape: add patches-5.4 Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu --- ...x2160-PCS-PHY-definitions-for-10GBase-KR-.patch | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch (limited to 'target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch') diff --git a/target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch b/target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch new file mode 100644 index 0000000000..22b2b64d79 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch @@ -0,0 +1,57 @@ +From c1619d9de2da093a585426e9cef353ca1789236d Mon Sep 17 00:00:00 2001 +From: Florinel Iordache +Date: Mon, 5 Nov 2018 17:02:19 +0200 +Subject: [PATCH] arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and + 40GBase-KR backplane modes + +Signed-off-by: Florinel Iordache +--- + arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +@@ -162,3 +162,43 @@ + &usb1 { + status = "okay"; + }; ++ ++&pcs_mdio1 { ++ pcs_phy1: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ backplane-mode = "40gbase-kr"; ++ reg = <0x0>; ++ fsl,lane-handle = <&serdes1>; ++ fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */ ++ }; ++}; ++ ++&pcs_mdio2 { ++ pcs_phy2: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ backplane-mode = "40gbase-kr"; ++ reg = <0x0>; ++ fsl,lane-handle = <&serdes1>; ++ fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */ ++ }; ++}; ++ ++&pcs_mdio3 { ++ pcs_phy3: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ backplane-mode = "10gbase-kr"; ++ reg = <0x0>; ++ fsl,lane-handle = <&serdes1>; ++ fsl,lane-reg = <0xF00 0x100>; /* lane H */ ++ }; ++}; ++ ++&pcs_mdio4 { ++ pcs_phy4: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ backplane-mode = "10gbase-kr"; ++ reg = <0x0>; ++ fsl,lane-handle = <&serdes1>; ++ fsl,lane-reg = <0xE00 0x100>; /* lane G */ ++ }; ++}; -- cgit v1.2.3