From c6c731fe311f7da42777ffd31804a4f6aa3f8e19 Mon Sep 17 00:00:00 2001 From: Yutang Jiang Date: Sat, 29 Oct 2016 00:14:32 +0800 Subject: layerscape: add 64b/32b target for ls1043ardb device Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang --- ...le-add-support-to-map-cacheable-and-non-s.patch | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch (limited to 'target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch') diff --git a/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch b/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch new file mode 100644 index 0000000000..841d5efd07 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch @@ -0,0 +1,22 @@ +From 1d6d5b6d2363cf5a0d175f086209fb208692ec00 Mon Sep 17 00:00:00 2001 +From: Haiying Wang +Date: Sat, 8 Aug 2015 07:25:02 -0400 +Subject: [PATCH 35/70] arm64/pgtable: add support to map cacheable and non + shareable memory + +Signed-off-by: Haiying Wang +--- + arch/arm64/include/asm/pgtable.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/include/asm/pgtable.h ++++ b/arch/arm64/include/asm/pgtable.h +@@ -392,6 +392,8 @@ static inline int has_transparent_hugepa + #define pgprot_cached(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ + PTE_PXN | PTE_UXN) ++#define pgprot_cached_ns(prot) \ ++ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED) + #define pgprot_device(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) + #define __HAVE_PHYS_MEM_ACCESS_PROT -- cgit v1.2.3