From c6c731fe311f7da42777ffd31804a4f6aa3f8e19 Mon Sep 17 00:00:00 2001 From: Yutang Jiang Date: Sat, 29 Oct 2016 00:14:32 +0800 Subject: layerscape: add 64b/32b target for ls1043ardb device Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang --- ...pdate-address-cells-and-reg-properties-of.patch | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch (limited to 'target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch') diff --git a/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch b/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch new file mode 100644 index 0000000000..20cf8522a7 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch @@ -0,0 +1,141 @@ +From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001 +From: Alison Wang +Date: Fri, 8 Jul 2016 10:50:46 +0800 +Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of + cpu nodes + +commit 67161e229a59faf81732892b45a9ab3bae62ea18 +[context adjustment] + +MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and +LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, +since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update +the #address-cells and reg properties accordingly. + +Signed-off-by: Alison Wang +Integrated-by: Zhao Qiang +--- + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++----- + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 +++++++++--------- + 2 files changed, 14 insertions(+), 14 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +@@ -51,7 +51,7 @@ + #size-cells = <2>; + + cpus { +- #address-cells = <2>; ++ #address-cells = <1>; + #size-cells = <0>; + + /* +@@ -63,28 +63,28 @@ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; +- reg = <0x0 0x0>; ++ reg = <0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; +- reg = <0x0 0x1>; ++ reg = <0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; +- reg = <0x0 0x2>; ++ reg = <0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; +- reg = <0x0 0x3>; ++ reg = <0x3>; + clocks = <&clockgen 1 0>; + }; + }; +--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +@@ -51,7 +51,7 @@ + #size-cells = <2>; + + cpus { +- #address-cells = <2>; ++ #address-cells = <1>; + #size-cells = <0>; + + /* +@@ -65,56 +65,56 @@ + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x0>; ++ reg = <0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x1>; ++ reg = <0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x100>; ++ reg = <0x100>; + clocks = <&clockgen 1 1>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; ++ reg = <0x101>; + clocks = <&clockgen 1 1>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x200>; ++ reg = <0x200>; + clocks = <&clockgen 1 2>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x201>; ++ reg = <0x201>; + clocks = <&clockgen 1 2>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x300>; ++ reg = <0x300>; + clocks = <&clockgen 1 3>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x301>; ++ reg = <0x301>; + clocks = <&clockgen 1 3>; + }; + }; -- cgit v1.2.3