From 3ae5da5adce90443426a477784e68cd9d49ded06 Mon Sep 17 00:00:00 2001 From: Rui Salvaterra Date: Thu, 18 Nov 2021 18:24:32 +0000 Subject: kernel: bump 5.10 to 5.10.80 Deleted (upstreamed): ath79/patches-5.10/921-serial-core-add-support-for-boot-console-with-arbitr.patch [1] bcm53xx/patches-5.10/033-v5.15-0012-ARM-dts-BCM5301X-Fix-memory-nodes-names.patch [2] lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch [3] lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch [4] lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch [5] lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch [6] Manually rebased: ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=47462c5e600fbaffd755cd13dedd80d04e41ff83 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=2fde76df1885a6bec04317e457121326070450eb [3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=9b366f5221d8aa64b22f35be137a5749326444ce [4] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=5af57ce8a6155fe3e4270d28d171abf8903bebc0 [5] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=b92a5df2c7adc79a57481445f67de0c1c716581f [6] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.80&id=6b72caabc47011d03f44064452b2c65e8ed18326 Signed-off-by: Rui Salvaterra --- ...-xway-Keep-the-driver-compatible-with-on-.patch | 68 ---------------------- ...PS-lantiq-dma-add-small-delay-after-reset.patch | 32 ---------- ...antiq-dma-reset-correct-number-of-channel.patch | 68 ---------------------- ...-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch | 41 ------------- .../lantiq/patches-5.10/0152-lantiq-VPE.patch | 2 +- 5 files changed, 1 insertion(+), 210 deletions(-) delete mode 100644 target/linux/lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch delete mode 100644 target/linux/lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch delete mode 100644 target/linux/lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch delete mode 100644 target/linux/lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch (limited to 'target/linux/lantiq') diff --git a/target/linux/lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch b/target/linux/lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch deleted file mode 100644 index 4f23cc94d7..0000000000 --- a/target/linux/lantiq/patches-5.10/0016-mtd-rawnand-xway-Keep-the-driver-compatible-with-on-.patch +++ /dev/null @@ -1,68 +0,0 @@ -From ae9a2ac4d283b2925a97523a05ea024499329c16 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Wed, 29 Sep 2021 00:22:58 +0200 -Subject: [PATCH] mtd: rawnand: xway: Keep the driver compatible with on-die - ECC engines - -Following the introduction of the generic ECC engine infrastructure, it -was necessary to reorganize the code and move the ECC configuration in -the ->attach_chip() hook. Failing to do that properly lead to a first -series of fixes supposed to stabilize the situation. Unfortunately, this -only fixed the use of software ECC engines, preventing any other kind of -engine to be used, including on-die ones. - -It is now time to (finally) fix the situation by ensuring that we still -provide a default (eg. software ECC) but will still support different -ECC engines such as on-die ECC engines if properly described in the -device tree. - -There are no changes needed on the core side in order to do this, but we -just need to leverage the logic there which allows: -1- a subsystem default (set to Host engines in the raw NAND world) -2- a driver specific default (here set to software ECC engines) -3- any type of engine requested by the user (ie. described in the DT) - -As the raw NAND subsystem has not yet been fully converted to the ECC -engine infrastructure, in order to provide a default ECC engine for this -driver we need to set chip->ecc.engine_type *before* calling -nand_scan(). During the initialization step, the core will consider this -entry as the default engine for this driver. This value may of course -be overloaded by the user if the usual DT properties are provided. - -Fixes: d525914b5bd8 ("mtd: rawnand: xway: Move the ECC initialization to ->attach_chip()") -Cc: stable@vger.kernel.org -Cc: Jan Hoffmann -Cc: Kestrel seventyfour -Signed-off-by: Miquel Raynal ---- - drivers/mtd/nand/raw/xway_nand.c | 12 +++++++++--- - 1 file changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -148,9 +148,8 @@ static void xway_write_buf(struct nand_c - - static int xway_attach_chip(struct nand_chip *chip) - { -- chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; -- -- if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) -+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && -+ chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) - chip->ecc.algo = NAND_ECC_ALGO_HAMMING; - - return 0; -@@ -219,6 +218,13 @@ static int xway_nand_probe(struct platfo - | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P - | cs_flag, EBU_NAND_CON); - -+ /* -+ * This driver assumes that the default ECC engine should be TYPE_SOFT. -+ * Set ->engine_type before registering the NAND devices in order to -+ * provide a driver specific default value. -+ */ -+ data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; -+ - /* Scan to find existence of the device */ - err = nand_scan(&data->chip, 1); - if (err) diff --git a/target/linux/lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch b/target/linux/lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch deleted file mode 100644 index 05227c8f89..0000000000 --- a/target/linux/lantiq/patches-5.10/0110-MIPS-lantiq-dma-add-small-delay-after-reset.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 497acc03cd3918baabe25d46e30c5c62b998e24d Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sat, 19 Jun 2021 13:38:12 +0200 -Subject: [PATCH 1/5] MIPS: lantiq: dma: add small delay after reset - -Reading the DMA registers immediately after the reset causes -Data Bus Error. Adding a small delay fixes this problem. - -Signed-off-by: Aleksander Jan Bajkowski ---- - arch/mips/lantiq/xway/dma.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -221,6 +222,8 @@ ltq_dma_init(struct platform_device *pde - clk_enable(clk); - ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); - -+ usleep_range(1, 10); -+ - /* disable all interrupts */ - ltq_dma_w32(0, LTQ_DMA_IRNEN); - diff --git a/target/linux/lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch b/target/linux/lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch deleted file mode 100644 index 5d1862d576..0000000000 --- a/target/linux/lantiq/patches-5.10/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch +++ /dev/null @@ -1,68 +0,0 @@ -From d31260c2f6a5cdddb052ab7cb09560eb23ce6597 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Thu, 15 Apr 2021 21:28:24 +0200 -Subject: [PATCH 2/5] MIPS: lantiq: dma: reset correct number of channel - -Different SoCs have a different number of channels, e.g .: -* amazon-se has 10 channels, -* danube+ar9 have 20 channels, -* vr9 has 28 channels, -* ar10 has 24 channels. - -We can read the ID register and, depending on the reported -number of channels, reset the appropriate number of channels. - -Signed-off-by: Aleksander Jan Bajkowski ---- - arch/mips/lantiq/xway/dma.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -30,6 +30,7 @@ - #define LTQ_DMA_PCTRL 0x44 - #define LTQ_DMA_IRNEN 0xf4 - -+#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */ - #define DMA_DESCPT BIT(3) /* descriptor complete irq */ - #define DMA_TX BIT(8) /* TX channel direction */ - #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ -@@ -40,7 +41,6 @@ - #define DMA_POLL BIT(31) /* turn on channel polling */ - #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ - #define DMA_2W_BURST BIT(1) /* 2 word burst length */ --#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ - #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ - #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ - -@@ -206,7 +206,7 @@ ltq_dma_init(struct platform_device *pde - { - struct clk *clk; - struct resource *res; -- unsigned id; -+ unsigned int id, nchannels; - int i; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -@@ -228,17 +228,18 @@ ltq_dma_init(struct platform_device *pde - ltq_dma_w32(0, LTQ_DMA_IRNEN); - - /* reset/configure each channel */ -- for (i = 0; i < DMA_MAX_CHANNEL; i++) { -+ id = ltq_dma_r32(LTQ_DMA_ID); -+ nchannels = ((id & DMA_ID_CHNR) >> 20); -+ for (i = 0; i < nchannels; i++) { - ltq_dma_w32(i, LTQ_DMA_CS); - ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); - ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); - ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); - } - -- id = ltq_dma_r32(LTQ_DMA_ID); - dev_info(&pdev->dev, - "Init done - hw rev: %X, ports: %d, channels: %d\n", -- id & 0x1f, (id >> 16) & 0xf, id >> 20); -+ id & 0x1f, (id >> 16) & 0xf, nchannels); - - return 0; - } diff --git a/target/linux/lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch b/target/linux/lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch deleted file mode 100644 index 67423d2e97..0000000000 --- a/target/linux/lantiq/patches-5.10/0112-MIPS-lantiq-dma-fix-burst-length-for-DEU.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 7d9ea9052d6680d2910b8b005c397d95b3a8b012 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 7 Apr 2021 21:04:39 +0200 -Subject: [PATCH 3/5] MIPS: lantiq: dma: fix burst length for DEU - -The current definition of 2W burst length is invalid. -This patch fixes it. Current downstream DEU driver doesn't -use DMA. An incorrect burst length value doesn't cause any -errors. This patch also adds other burst length values. - -Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support") -Signed-off-by: Aleksander Jan Bajkowski ---- - arch/mips/lantiq/xway/dma.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -40,7 +40,11 @@ - #define DMA_IRQ_ACK 0x7e /* IRQ status register */ - #define DMA_POLL BIT(31) /* turn on channel polling */ - #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ --#define DMA_2W_BURST BIT(1) /* 2 word burst length */ -+#define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */ -+#define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */ -+#define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */ -+#define DMA_TX_BURST_SHIFT 4 /* tx burst shift */ -+#define DMA_RX_BURST_SHIFT 2 /* rx burst shift */ - #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ - #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ - -@@ -191,7 +195,8 @@ ltq_dma_init_port(int p) - break; - - case DMA_PORT_DEU: -- ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), -+ ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) | -+ (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), - LTQ_DMA_PCTRL); - break; - diff --git a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch index 2444f12df8..49285500bf 100644 --- a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch +++ b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -2430,6 +2430,12 @@ config MIPS_VPE_LOADER +@@ -2431,6 +2431,12 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. -- cgit v1.2.3