From dfdbdac2e5c20fffd2eb37b35501aa0654795278 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Wed, 9 Jan 2008 02:36:02 +0000 Subject: Consolidated fsg3 support into a single patch, identical to the one in the nlsu2-linux kernel repository SVN-Revision: 10151 --- .../105-ixp4xx_fsg_board_support.patch | 545 +++++++++++++++++++++ 1 file changed, 545 insertions(+) create mode 100644 target/linux/ixp4xx/patches-2.6.23/105-ixp4xx_fsg_board_support.patch (limited to 'target/linux/ixp4xx/patches-2.6.23/105-ixp4xx_fsg_board_support.patch') diff --git a/target/linux/ixp4xx/patches-2.6.23/105-ixp4xx_fsg_board_support.patch b/target/linux/ixp4xx/patches-2.6.23/105-ixp4xx_fsg_board_support.patch new file mode 100644 index 0000000000..668416f294 --- /dev/null +++ b/target/linux/ixp4xx/patches-2.6.23/105-ixp4xx_fsg_board_support.patch @@ -0,0 +1,545 @@ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-pci.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-pci.c 2008-01-09 12:49:07.000000000 +1030 +@@ -0,0 +1,71 @@ ++/* ++ * arch/arch/mach-ixp4xx/fsg-pci.c ++ * ++ * FSG board-level PCI initialization ++ * ++ * Author: Rod Whitby ++ * Maintainer: http://www.nslu2-linux.org/ ++ * ++ * based on ixdp425-pci.c: ++ * Copyright (C) 2002 Intel Corporation. ++ * Copyright (C) 2003-2004 MontaVista Software, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++void __init fsg_pci_preinit(void) ++{ ++ set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW); ++ set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW); ++ set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ static int pci_irq_table[FSG_PCI_IRQ_LINES] = { ++ IRQ_FSG_PCI_INTC, ++ IRQ_FSG_PCI_INTB, ++ IRQ_FSG_PCI_INTA, ++ }; ++ ++ int irq = -1; ++ slot = slot - 11; ++ ++ if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && ++ pin >= 1 && pin <= FSG_PCI_IRQ_LINES) { ++ irq = pci_irq_table[(slot - 1)]; ++ } ++ printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, irq); ++ ++ return irq; ++} ++ ++struct hw_pci fsg_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = fsg_pci_preinit, ++ .swizzle = pci_std_swizzle, ++ .setup = ixp4xx_setup, ++ .scan = ixp4xx_scan_bus, ++ .map_irq = fsg_map_irq, ++}; ++ ++int __init fsg_pci_init(void) ++{ ++ if (machine_is_fsg()) ++ pci_common_init(&fsg_pci); ++ return 0; ++} ++ ++subsys_initcall(fsg_pci_init); +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-setup.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-setup.c 2008-01-09 12:49:07.000000000 +1030 +@@ -0,0 +1,220 @@ ++/* ++ * arch/arm/mach-ixp4xx/fsg-setup.c ++ * ++ * FSG board-setup ++ * ++ * based ixdp425-setup.c: ++ * Copyright (C) 2003-2004 MontaVista Software, Inc. ++ * ++ * Author: Rod Whitby ++ * Maintainers: http://www.nslu2-linux.org/ ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data fsg_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource fsg_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device fsg_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev.platform_data = &fsg_flash_data, ++ .num_resources = 1, ++ .resource = &fsg_flash_resource, ++}; ++ ++static struct i2c_gpio_platform_data fsg_i2c_gpio_data = { ++ .sda_pin = FSG_SDA_PIN, ++ .scl_pin = FSG_SCL_PIN, ++}; ++ ++static struct platform_device fsg_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &fsg_i2c_gpio_data, ++ }, ++}; ++ ++static struct resource fsg_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port fsg_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { } ++}; ++ ++static struct platform_device fsg_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = fsg_uart_data, ++ .num_resources = ARRAY_SIZE(fsg_uart_resources), ++ .resource = fsg_uart_resources, ++}; ++ ++static struct platform_device fsg_leds = { ++ .name = "fsg-led", ++ .id = -1, ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info fsg_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 4, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device fsg_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = fsg_plat_eth, ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = fsg_plat_eth + 1, ++ } ++}; ++ ++static struct platform_device *fsg_devices[] __initdata = { ++ &fsg_i2c_gpio, ++ &fsg_flash, ++ &fsg_leds, ++ &fsg_eth[0], ++ &fsg_eth[1], ++}; ++ ++static void fsg_power_off(void) ++{ ++ printk("Restarting system.\n"); ++ machine_restart(NULL); ++} ++ ++static void __init fsg_init(void) ++{ ++ uint8_t __iomem *f; ++ int i; ++ ++ ixp4xx_sys_init(); ++ ++ pm_power_off = fsg_power_off; ++ ++ fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ fsg_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ /* Configure CS2 for operation, 8bit and writable */ ++ *IXP4XX_EXP_CS2 = 0xbfff0002; ++ ++ /* This is only useful on a modified machine, but it is valuable ++ * to have it first in order to see debug messages, and so that ++ * it does *not* get removed if platform_add_devices fails! ++ */ ++ (void)platform_device_register(&fsg_uart); ++ ++ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices)); ++ ++ ++ /* ++ * Map in a portion of the flash and read the MAC addresses. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ if ((f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000))) { ++#ifdef __ARMEB__ ++ for (i = 0; i < 6; i++) { ++ fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i); ++ fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i); ++ } ++#else ++ fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0422 + 3); ++ fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0422 + 2); ++ fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0422 + 1); ++ fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0422 + 0); ++ fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0422 + 7); ++ fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0422 + 6); ++ ++ fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0422 + 3); ++ fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C0422 + 2); ++ fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C0422 + 1); ++ fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C0422 + 0); ++ fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C0422 + 7); ++ fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0422 + 6); ++#endif ++ iounmap(f); ++ } ++ printk(KERN_INFO "FSG: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 0\n", ++ fsg_plat_eth[0].hwaddr[0], fsg_plat_eth[0].hwaddr[1], ++ fsg_plat_eth[0].hwaddr[2], fsg_plat_eth[0].hwaddr[3], ++ fsg_plat_eth[0].hwaddr[4], fsg_plat_eth[0].hwaddr[5]); ++ printk(KERN_INFO "FSG: Using MAC address %.2x:%.2x:%.2x:%.2x:%.2x:%.2x for port 1\n", ++ fsg_plat_eth[1].hwaddr[0], fsg_plat_eth[1].hwaddr[1], ++ fsg_plat_eth[1].hwaddr[2], fsg_plat_eth[1].hwaddr[3], ++ fsg_plat_eth[1].hwaddr[4], fsg_plat_eth[1].hwaddr[5]); ++ ++} ++ ++MACHINE_START(FSG, "Freecom FSG-3") ++ /* Maintainer: www.nslu2-linux.org */ ++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, ++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .timer = &ixp4xx_timer, ++ .boot_params = 0x0100, ++ .init_machine = fsg_init, ++MACHINE_END ++ +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Kconfig +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/Kconfig 2008-01-09 12:49:04.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Kconfig 2008-01-09 12:49:07.000000000 +1030 +@@ -125,6 +125,15 @@ + depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435 + default y + ++config MACH_FSG ++ bool ++ prompt "Freecom FSG-3" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Freecom's ++ FSG-3 device. For more information on this platform ++ see http://www.nslu2-linux.org/wiki/FSG3/HomePage ++ + # + # Certain registers and IRQs are only enabled if supporting IXP465 CPUs + # +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Makefile +=================================================================== +--- linux-2.6.23.12-armeb.orig/arch/arm/mach-ixp4xx/Makefile 2008-01-09 12:49:04.000000000 +1030 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/Makefile 2008-01-09 12:49:07.000000000 +1030 +@@ -15,6 +15,7 @@ + obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o ++obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + + obj-y += common.o + +@@ -28,6 +29,7 @@ + obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o ++obj-$(CONFIG_MACH_FSG) += fsg-setup.o fsg-power.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/fsg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/fsg.h 2008-01-09 12:49:07.000000000 +1030 +@@ -0,0 +1,74 @@ ++/* ++ * include/asm-arm/arch-ixp4xx/fsg.h ++ * ++ * Freecom FSG-3 platform specific definitions ++ * ++ * Author: Rod Whitby ++ * Author: Tomasz Chmielewski ++ * Maintainers: http://www.nslu2-linux.org ++ * ++ * Based on coyote.h by ++ * Copyright 2004 (c) MontaVista, Software, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H__ ++#error "Do not include this directly, instead #include " ++#endif ++ ++#define FSG_SDA_PIN 12 ++#define FSG_SCL_PIN 13 ++ ++/* ++ * FSG PCI IRQs ++ */ ++#define FSG_PCI_MAX_DEV 3 ++#define FSG_PCI_IRQ_LINES 3 ++ ++ ++/* PCI controller GPIO to IRQ pin mappings */ ++#define FSG_PCI_INTA_PIN 6 ++#define FSG_PCI_INTB_PIN 7 ++#define FSG_PCI_INTC_PIN 5 ++ ++/* Buttons */ ++ ++#define FSG_SB_GPIO 4 ++#define FSG_RB_GPIO 9 ++#define FSG_UB_GPIO 10 ++ ++#define FSG_SB_IRQ IRQ_IXP4XX_GPIO4 ++#define FSG_RB_IRQ IRQ_IXP4XX_GPIO9 ++#define FSG_UB_IRQ IRQ_IXP4XX_GPIO10 ++ ++#define FSG_SB_BM (1L << FSG_SB_GPIO) ++#define FSG_RB_BM (1L << FSG_RB_GPIO) ++#define FSG_UB_BM (1L << FSG_UB_GPIO) ++ ++/* LEDs */ ++ ++#define FSG_LED_RING_GPIO 0 ++#define FSG_LED_SYNC_GPIO 1 ++#define FSG_LED_USB_GPIO 2 ++#define FSG_LED_SATA_GPIO 3 ++#define FSG_LED_WAN_GPIO 4 ++#define FSG_LED_WLAN_GPIO 5 ++ ++/* %%% REMOVE %%% ++#define FSG_PCI_SLOT0_PIN 6 ++#define FSG_PCI_SLOT1_PIN 7 ++ ++#define FSG_PCI_SLOT0_DEVID 14 ++#define FSG_PCI_SLOT1_DEVID 15 ++ ++#define FSG_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) ++#define FSG_IDE_BASE_VIRT 0xFFFE1000 ++#define FSG_IDE_REGION_SIZE 0x1000 ++ ++#define FSG_IDE_DATA_PORT 0xFFFE10E0 ++#define FSG_IDE_CTRL_PORT 0xFFFE10FC ++#define FSG_IDE_ERROR_PORT 0xFFFE10E2 ++*/ +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/hardware.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/hardware.h 2008-01-09 12:49:04.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/hardware.h 2008-01-09 12:49:07.000000000 +1030 +@@ -45,5 +45,6 @@ + #include "nslu2.h" + #include "nas100d.h" + #include "dsmg600.h" ++#include "fsg.h" + + #endif /* _ASM_ARCH_HARDWARE_H */ +Index: linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/irqs.h +=================================================================== +--- linux-2.6.23.12-armeb.orig/include/asm-arm/arch-ixp4xx/irqs.h 2008-01-09 12:49:04.000000000 +1030 ++++ linux-2.6.23.12-armeb/include/asm-arm/arch-ixp4xx/irqs.h 2008-01-09 12:49:07.000000000 +1030 +@@ -128,4 +128,17 @@ + #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 + #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 + ++/* ++ * Freecom FSG-3 Board IRQs ++ */ ++#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 ++#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 ++#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 ++ ++/* %%% REMOVE %%% ++#define IRQ_FSG_PCI_SLOT0 IRQ_IXP4XX_GPIO6 ++#define IRQ_FSG_PCI_SLOT1 IRQ_IXP4XX_GPIO7 ++#define IRQ_FSG_IDE IRQ_IXP4XX_GPIO5 ++*/ ++ + #endif +Index: linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-power.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.23.12-armeb/arch/arm/mach-ixp4xx/fsg-power.c 2008-01-09 12:49:07.000000000 +1030 +@@ -0,0 +1,87 @@ ++/* ++ * arch/arm/mach-ixp4xx/fsg-power.c ++ * ++ * FSG Power/Reset driver ++ * ++ * Copyright (C) 2008 Rod Whitby ++ * ++ * based on nslu2-power.c ++ * Copyright (C) 2005 Tower Technologies ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static irqreturn_t fsg_power_handler(int irq, void *dev_id) ++{ ++ /* Signal init to do the ctrlaltdel action, this will bypass init if ++ * it hasn't started and do a kernel_restart. ++ */ ++ ctrl_alt_del(); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t fsg_reset_handler(int irq, void *dev_id) ++{ ++ /* This is the paper-clip reset, it shuts the machine down directly. ++ */ ++ machine_power_off(); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init fsg_power_init(void) ++{ ++ if (!(machine_is_fsg())) ++ return 0; ++ ++ set_irq_type(FSG_RB_IRQ, IRQT_LOW); ++ set_irq_type(FSG_SB_IRQ, IRQT_LOW); ++ ++ if (request_irq(FSG_RB_IRQ, &fsg_reset_handler, ++ IRQF_DISABLED, "FSG reset button", NULL) < 0) { ++ ++ printk(KERN_DEBUG "Reset Button IRQ %d not available\n", ++ FSG_RB_IRQ); ++ ++ return -EIO; ++ } ++ ++ if (request_irq(FSG_SB_IRQ, &fsg_power_handler, ++ IRQF_DISABLED, "FSG power button", NULL) < 0) { ++ ++ printk(KERN_DEBUG "Power Button IRQ %d not available\n", ++ FSG_SB_IRQ); ++ ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static void __exit fsg_power_exit(void) ++{ ++ if (!(machine_is_fsg())) ++ return; ++ ++ free_irq(FSG_SB_IRQ, NULL); ++ free_irq(FSG_RB_IRQ, NULL); ++} ++ ++module_init(fsg_power_init); ++module_exit(fsg_power_exit); ++ ++MODULE_AUTHOR("Rod Whitby "); ++MODULE_DESCRIPTION("FSG Power/Reset driver"); ++MODULE_LICENSE("GPL"); -- cgit v1.2.3