From c52cd4d8c3ab1fd0db8806a5e37158e7022c1c40 Mon Sep 17 00:00:00 2001 From: Pavel Kubelun Date: Thu, 18 Jan 2018 19:45:15 +0300 Subject: ipq806x: fix EA8500 switch control EA8500 has pcie2 slot unequipped. By EA8500 hw design default pcie2 reset gpio (gpio63) is used to reset the switch. That's why enabling pcie2 brings the switch into a working state. So let's just control the gpio63 without enabling the pcie2 slot. We have to remove the pcie2_pins node so the gpio63 is not defined twice. Because pcie2 node has a reference to pcie2_pins we have to remove it as well. Signed-off-by: Pavel Kubelun [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann (cherry picked from commit 7f694ef3d9f1121c03935c330093c594b8437098) --- .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'target/linux/ipq806x/files-4.14/arch/arm/boot/dts') diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts index 2c8fe922f4..cd8fa633b1 100644 --- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts @@ -39,6 +39,10 @@ soc { pinmux@800000 { + + pinctrl-0 = <&switch_reset>; + pinctrl-names = "default"; + button_pins: button_pins { mux { pins = "gpio65", "gpio67", "gpio68"; @@ -66,6 +70,16 @@ }; }; + switch_reset: switch_reset_pins { + mux { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + mdio0_pins: mdio0_pins { mux { pins = "gpio0", "gpio1"; @@ -164,10 +178,6 @@ status = "ok"; }; - pcie2: pci@1b900000 { - status = "ok"; - }; - nand@1ac00000 { status = "ok"; @@ -404,3 +414,7 @@ }; }; }; + +/delete-node/ &pcie2_pins; +/delete-node/ &pcie2; + -- cgit v1.2.3