From 4943afd7818f56053231a5a7ae90e55da44f1f08 Mon Sep 17 00:00:00 2001 From: Chris Blake Date: Sat, 10 Mar 2018 10:59:18 +0100 Subject: ipq40xx: add Cisco Meraki MR33 Support This patch adds support for Cisco Meraki MR33 hardware highlights: SOC: IPQ4029 Quad-Core ARMv7 Processor rev 5 (v7l) Cortex-A7 DRAM: 256 MiB DDR3L-1600 @ 627 MHz Micron MT41K128M16JT-125IT NAND: 128 MiB SLC NAND Spansion S34ML01G200TFV00 (106 MiB usable) ETH: Qualcomm Atheros AR8035 Gigabit PHY (1 x LAN/WAN) + PoE WLAN1: QCA9887 (168c:0050) PCIe 1x1:1 802.11abgn ac Dualband VHT80 WLAN2: Qualcomm Atheros QCA4029 2.4GHz 802.11bgn 2:2x2 WLAN3: Qualcomm Atheros QCA4029 5GHz 802.11a/n/ac 2:2x2 VHT80 LEDS: 1 x Programmable RGB+White Status LED (driven by Ti LP5562 on i2c-1) 1 x Orange LED Fault Indicator (shared with LP5562) 2 x LAN Activity / Speed LEDs (On the RJ45 Port) BUTTON: one Reset button MISC: Bluetooth LE Ti cc2650 PG2.3 4x4mm - BL_CONFIG at 0x0001FFD8 AT24C64 8KiB EEPROM Kensington Lock Serial: WARNING: The serial port needs a TTL/RS-232 3V3 level converter! The Serial setting is 115200-8-N-1. The board has a populated 1x4 0.1" header with half-height/low profile pins. The pinout is: VCC (little white arrow), RX, TX, GND. Flashing needs a serial adaptor, as well as patched ubootwrite utility (needs Little-Endian support). And a modified u-boot (enabled Ethernet). Meraki's original u-boot source can be found in: Add images to do an installation via bootloader: 0. open up the MR33 and connect the serial console. 1. start the 2nd stage bootloader transfer from client pc: # ubootwrite.py --write=mr33-uboot.bin (The ubootwrite tool will interrupt the boot-process and hence it needs to listen for cues. If the connection is bad (due to the low-profile pins), the tool can fail multiple times and in weird ways. If you are not sure, just use a terminal program and see what the device is doing there. 2. power on the MR33 (with ethernet + serial cables attached) Warning: Make sure you do this in a private LAN that has no connection to the internet. - let it upload the u-boot this can take 250-300 seconds - 3. use a tftp client (in binary mode!) on your PC to upload the sysupgrade.bin (the u-boot is listening on 192.168.1.1) # tftp 192.168.1.1 binary put openwrt-ipq40xx-meraki_mr33-squashfs-sysupgrade.bin 4. wait for it to reboot 5. connect to your MR33 via ssh on 192.168.1.1 For more detailed instructions, please take a look at the: "Flashing Instructions for the MR33" PDF. This can be found on the wiki: (A link to the mr33-uboot.bin + the modified ubootwrite is also there) Thanks to Jerome C. for sending an MR33 to Chris. Signed-off-by: Chris Blake Signed-off-by: Mathias Kresin Signed-off-by: Christian Lamparter --- .../arch/arm/boot/dts/qcom-ipq4029-mr33.dts | 403 +++++++++++++++++++++ 1 file changed, 403 insertions(+) create mode 100644 target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-mr33.dts (limited to 'target/linux/ipq40xx/files-4.14/arch/arm') diff --git a/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-mr33.dts b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-mr33.dts new file mode 100644 index 0000000000..9c1ef4f020 --- /dev/null +++ b/target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-mr33.dts @@ -0,0 +1,403 @@ +/* + * Device Tree Source for Meraki MR33 (Stinkbug) + * + * Copyright (C) 2017 Chris Blake + * Copyright (C) 2017 Christian Lamparter + * + * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +#include "qcom-ipq4019.dtsi" +#include "qcom-ipq4019-bus.dtsi" +#include +#include +#include + +/ { + model = "Meraki MR33 Access Point"; + compatible = "meraki,mr33", "qcom,ipq4019"; + + aliases { + led-boot = &status_green; + led-failsafe = &status_red; + led-running = &status_green; + led-upgrade = &power_orange; + }; + + /* Do we really need this defined? */ + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + tz_apps@87b80000 { + reg = <0x87b80000 0x280000>; + reusable; + }; + + smem@87e00000 { + reg = <0x87e00000 0x080000>; + no-map; + }; + + tz@87e80000 { + reg = <0x87e80000 0x180000>; + no-map; + }; + }; + + soc { + mdio@90000 { + status = "okay"; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy-reset-gpio = <&tlmm 47 0>; + /delete-node/ ethernet-phy@0; + /delete-node/ ethernet-phy@2; + /delete-node/ ethernet-phy@3; + /delete-node/ ethernet-phy@4; + }; + + /* It is a 56-bit counter that supplies the count to the ARM arch + timers and without upstream driver */ + counter@4a1000 { + compatible = "qcom,qca-gcnt"; + reg = <0x4a1000 0x4>; + }; + + ess_tcsr@1953000 { + compatible = "qcom,tcsr"; + reg = <0x1953000 0x1000>; + qcom,ess-interface-select = ; + }; + + tcsr@1949000 { + compatible = "qcom,tcsr"; + reg = <0x1949000 0x100>; + qcom,wifi_glb_cfg = ; + }; + + tcsr@1957000 { + compatible = "qcom,tcsr"; + reg = <0x1957000 0x100>; + qcom,wifi_noc_memtype_m0_m2 = ; + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "ti,cc2650"; + enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + }; + }; + + crypto@8e3a000 { + status = "okay"; + }; + + watchdog@b017000 { + status = "okay"; + }; + + ess-switch@c000000 { + switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */ + switch_lan_bmp = <0x0>; /* lan port bitmap */ + switch_wan_bmp = <0x10>; /* wan port bitmap */ + }; + + edma@c080000 { + qcom,single-phy; + qcom,num_gmac = <1>; + phy-mode = "rgmii-rxid"; + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_orange: power { + label = "mr33:orange:power"; + gpios = <&tlmm 49 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; +}; + +&blsp_dma { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&gmac0 { + qcom,phy_mdio_addr = <1>; + qcom,poll_required = <1>; + vlan_tag = <0 0x20>; +}; + +&i2c_0 { + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + status = "okay"; + at24@50 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x50>; + read-only; /* This holds our MAC & Meraki board-data */ + }; +}; + +&i2c_1 { + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; + + lp5562@30 { + enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>; + compatible = "ti,lp5562"; + clock-mode = /bits/8 <2>; + reg = <0x30>; + + /* RGB led */ + status_red: chan0 { + chan-name = "mr33:red:status"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + status_green: chan1 { + chan-name = "mr33:green:status"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan2 { + chan-name = "mr33:blue:status"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan3 { + chan-name = "mr33:white:status"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + }; +}; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; + + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "sbl1"; + reg = <0x000000000000 0x000000100000>; + read-only; + }; + partition@1 { + label = "mibib"; + reg = <0x000000100000 0x000000100000>; + read-only; + }; + partition@2 { + label = "bootconfig"; + reg = <0x000000200000 0x000000100000>; + read-only; + }; + partition@3 { + label = "qsee"; + reg = <0x000000300000 0x000000100000>; + read-only; + }; + partition@4 { + label = "qsee_alt"; + reg = <0x000000400000 0x000000100000>; + read-only; + }; + partition@5 { + label = "cdt"; + reg = <0x000000500000 0x000000080000>; + read-only; + }; + partition@6 { + label = "cdt_alt"; + reg = <0x000000580000 0x000000080000>; + read-only; + }; + partition@7 { + label = "ddrparams"; + reg = <0x000000600000 0x000000080000>; + read-only; + }; + partition@8 { + label = "u-boot"; + reg = <0x000000700000 0x000000200000>; + read-only; + }; + partition@9 { + label = "u-boot-backup"; + reg = <0x000000900000 0x000000200000>; + read-only; + }; + partition@10 { + label = "ART"; + reg = <0x000000b00000 0x000000080000>; + read-only; + }; + partition@11 { + label = "ubi"; + reg = <0x000000c00000 0x000007000000>; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; +}; + +&qpic_bam { + status = "okay"; +}; + +&tlmm { + /* + * GPIO43 should be 0/1 whenever the unit is + * powered through PoE or AC-Adapter. + * That said, playing with this seems to + * reset the AP. + */ + + mdio_pins: mdio_pinmux { + mux_1 { + pins = "gpio6"; + function = "mdio"; + bias-pull-up; + }; + mux_2 { + pins = "gpio7"; + function = "mdc"; + bias-pull-up; + }; + }; + + serial_0_pins: serial_pinmux { + mux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + serial_1_pins: serial1_pinmux { + mux { + /* We use the i2c-0 pins for serial_1 */ + pins = "gpio8", "gpio9"; + function = "blsp_uart1"; + bias-disable; + }; + }; + + i2c_0_pins: i2c_0_pinmux { + pinmux { + function = "blsp_i2c0"; + pins = "gpio20", "gpio21"; + }; + pinconf { + pins = "gpio20", "gpio21"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c_1_pins: i2c_1_pinmux { + pinmux { + function = "blsp_i2c1"; + pins = "gpio34", "gpio35"; + }; + pinconf { + pins = "gpio34", "gpio35"; + drive-strength = <16>; + bias-disable; + }; + }; + + nand_pins: nand_pins { + /* + * There are 18 pins. 15 pins are common between LCD and NAND. + * The QPIC controller arbitrates between LCD and NAND. Of the + * remaining 4, 2 are for NAND and 2 are for LCD exclusively. + * + * The meraki source hints that the bluetooth module claims + * pin 52 as well. But sadly, there's no data whenever this + * is a NAND or LCD exclusive pin or not. + */ + + pullups { + pins = "gpio52", "gpio53", "gpio58", + "gpio59"; + function = "qpic"; + bias-pull-up; + }; + + pulldowns { + pins = "gpio54", "gpio55", "gpio56", + "gpio57", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", + "gpio65", "gpio66", "gpio67", + "gpio68", "gpio69"; + function = "qpic"; + bias-pull-down; + }; + }; +}; + +&wifi0 { + status = "okay"; + /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */ +}; + +&wifi1 { + status = "okay"; + /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */ +}; -- cgit v1.2.3