From 3f059f58dba3a1fb9e1e5035b437273f095040f6 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Fri, 20 Sep 2013 01:59:32 +0000 Subject: imx6: update PCIe driver Signed-off-by: Tim Harvey Signed-off-by: Luka Perkov SVN-Revision: 38080 --- ...6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch (limited to 'target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch') diff --git a/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch new file mode 100644 index 0000000000..0e65fb9a2f --- /dev/null +++ b/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch @@ -0,0 +1,37 @@ +Subject: [v6,2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition +From: Sean Cross + +PCIe requires additional bits be defined for GPR8 and GPR12. + +Signed-off-by: Sean Cross +--- + include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +index b6bdcd6..e00e9f3 100644 +--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h ++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +@@ -241,6 +241,12 @@ + + #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + ++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) ++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) ++ + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) + #define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +@@ -273,7 +279,9 @@ + #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) + #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) + #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) ++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) + #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) ++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) + + #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) + #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) -- cgit v1.2.3