From fdac05b7416b7355f565065bdbc158e0ede7133e Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 31 Jul 2020 19:41:26 +0200 Subject: kernel: Update kernel 4.19 to version 4.19.138 Compile and run tested on lantiq/xrx200 Signed-off-by: Hauke Mehrtens --- ...ssing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch | 61 ---------------------- .../810-pci_disable_common_quirks.patch | 6 +-- 2 files changed, 3 insertions(+), 64 deletions(-) delete mode 100644 target/linux/generic/pending-4.19/350-MIPS-Add-missing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch (limited to 'target/linux/generic/pending-4.19') diff --git a/target/linux/generic/pending-4.19/350-MIPS-Add-missing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch b/target/linux/generic/pending-4.19/350-MIPS-Add-missing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch deleted file mode 100644 index 92a22bc655..0000000000 --- a/target/linux/generic/pending-4.19/350-MIPS-Add-missing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch +++ /dev/null @@ -1,61 +0,0 @@ -From db4603e30effd74d4adb6bcdf73072b2c06fafcd Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 3 Jul 2020 00:07:15 +0200 -Subject: [PATCH] MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPen - -This resolves the hazard between the mtc0 in the change_c0_status() and -the mfc0 in configure_exception_vector(). Without resolving this hazard -configure_exception_vector() could read an old value and would restore -this old value again. This would revert the changes change_c0_status() -did. I checked this by printing out the read_c0_status() at the end of -per_cpu_trap_init() and the ST0_MX is not set without this patch. - -The hazard is documented in the MIPS Architecture Reference Manual Vol. -III: MIPS32/microMIPS32 Privileged Resource Architecture (MD00088), rev -6.03 table 8.1 which includes: - - Producer | Consumer | Hazard - ----------|----------|---------------------------- - mtc0 | mfc0 | any coprocessor 0 register - -I saw this hazard on an Atheros AR9344 rev 2 SoC with a MIPS 74Kc CPU. -There the change_c0_status() function would activate the DSPen by -setting ST0_MX in the c0_status register. This was reverted and then the -system got a DSP exception when the DSP registers were saved in -save_dsp() in the first process switch. The crash looks like this: - -[ 0.089999] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) -[ 0.097796] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) -[ 0.107070] Kernel panic - not syncing: Unexpected DSP exception -[ 0.113470] Rebooting in 1 seconds.. - -We saw this problem in OpenWrt only on the MIPS 74Kc based Atheros SoCs, -not on the 24Kc based SoCs. We only saw it with kernel 5.4 not with -kernel 4.19, in addition we had to use GCC 8.4 or 9.X, with GCC 8.3 it -did not happen. - -In the kernel I bisected this problem to commit 9012d011660e ("compiler: -allow all arches to enable CONFIG_OPTIMIZE_INLINING"), but when this was -reverted it also happened after commit 172dcd935c34b ("MIPS: Always -allocate exception vector for MIPSr2+"). - -Commit 0b24cae4d535 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.") -does similar changes to a different file. I am not sure if there are -more places affected by this problem. - -Signed-off-by: Hauke Mehrtens -Cc: ---- - arch/mips/kernel/traps.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -2096,6 +2096,7 @@ static void configure_status(void) - - change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, - status_set); -+ back_to_back_c0_hazard(); - } - - unsigned int hwrena; diff --git a/target/linux/generic/pending-4.19/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-4.19/810-pci_disable_common_quirks.patch index 669229c620..c757aeeaad 100644 --- a/target/linux/generic/pending-4.19/810-pci_disable_common_quirks.patch +++ b/target/linux/generic/pending-4.19/810-pci_disable_common_quirks.patch @@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos /* * The Mellanox Tavor device gives false positive parity errors. Mark this * device with a broken_parity_status to allow PCI scanning code to "skip" -@@ -3213,6 +3214,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I +@@ -3226,6 +3227,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); @@ -42,7 +42,7 @@ Signed-off-by: Gabor Juhos /* * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. * To work around this, query the size it should be configured to by the -@@ -3238,6 +3241,8 @@ static void quirk_intel_ntb(struct pci_d +@@ -3251,6 +3254,8 @@ static void quirk_intel_ntb(struct pci_d DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); @@ -51,7 +51,7 @@ Signed-off-by: Gabor Juhos /* * Some BIOS implementations leave the Intel GPU interrupts enabled, even * though no one is handling them (e.g., if the i915 driver is never -@@ -3276,6 +3281,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN +@@ -3289,6 +3294,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); -- cgit v1.2.3