From f58dcb59c6621a9c587e3ce9705c88de6239b47e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 19 Apr 2013 12:39:40 +0000 Subject: kernel: backport SSB/BCMA changes in preparation for a compat-wireless update Signed-off-by: Felix Fietkau SVN-Revision: 36367 --- .../generic/patches-3.7/025-bcma_backport.patch | 139 +++++++++++++++++---- 1 file changed, 117 insertions(+), 22 deletions(-) (limited to 'target/linux/generic/patches-3.7/025-bcma_backport.patch') diff --git a/target/linux/generic/patches-3.7/025-bcma_backport.patch b/target/linux/generic/patches-3.7/025-bcma_backport.patch index 4bd1b11f39..94be7ae8e5 100644 --- a/target/linux/generic/patches-3.7/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.7/025-bcma_backport.patch @@ -87,12 +87,12 @@ #include static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked return value; } -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) -+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) { - u32 leddc_on = 10; - u32 leddc_off = 90; @@ -102,6 +102,7 @@ - if (cc->setup_done) + return 20000000; +} ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ @@ -211,7 +212,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -248,7 +249,7 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ +@@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -262,6 +263,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { @@ -275,6 +277,7 @@ + + return res; } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); +/* + * If the bit is set to 0, chipcommon controlls this GPIO, @@ -351,7 +354,7 @@ } #ifdef CONFIG_BCMA_DRIVER_MIPS -@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -363,7 +366,7 @@ bcma_cc_write32(cc, BCMA_CC_CORECTL, --- a/drivers/bcma/driver_chipcommon_nflash.c +++ b/drivers/bcma/driver_chipcommon_nflash.c -@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc +@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc } cc->nflash.present = true; @@ -390,7 +393,7 @@ void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) { -@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct +@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct } } @@ -410,7 +413,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -165,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_pmu_workarounds(cc); } @@ -419,7 +422,44 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -193,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -428,7 +468,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -222,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -445,7 +485,7 @@ { u32 tmp, ndiv, p1div, p2div; u32 clock; -@@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct +@@ -260,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -454,7 +494,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(str +@@ -268,40 +288,42 @@ static u32 bcma_pmu_get_clockcontrol(str case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: @@ -508,7 +548,7 @@ BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: -@@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -316,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -522,6 +562,51 @@ } static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, +@@ -365,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -386,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -419,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -453,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -489,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", --- a/drivers/bcma/driver_chipcommon_sflash.c +++ b/drivers/bcma/driver_chipcommon_sflash.c @@ -12,7 +12,7 @@ @@ -577,7 +662,7 @@ { 0 }, }; -@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc +@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc break; } break; @@ -586,7 +671,7 @@ default: for (e = bcma_sflash_st_tbl; e->name; e++) { if (e->id == id) -@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc +@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc return -ENOTSUPP; } @@ -800,7 +885,7 @@ for (i = 0; i <= 6; i++) printk(" %s%s", irq_name[i], i == irq ? "*" : " "); printk("\n"); -@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -1252,7 +1337,15 @@ /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -510,6 +513,7 @@ struct bcma_chipcommon_pmu { +@@ -101,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -510,6 +514,7 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -1260,7 +1353,7 @@ u8 buswidth; u32 window; u32 window_size; -@@ -532,6 +536,7 @@ struct mtd_info; +@@ -532,6 +537,7 @@ struct mtd_info; struct bcma_nflash { bool present; @@ -1268,7 +1361,7 @@ struct mtd_info *mtd; }; -@@ -552,6 +557,7 @@ struct bcma_drv_cc { +@@ -552,6 +558,7 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -1276,7 +1369,7 @@ /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; struct bcma_chipcommon_pmu pmu; -@@ -567,6 +573,14 @@ struct bcma_drv_cc { +@@ -567,6 +574,14 @@ struct bcma_drv_cc { int nr_serial_ports; struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ @@ -1291,7 +1384,7 @@ }; /* Register access */ -@@ -583,14 +597,14 @@ struct bcma_drv_cc { +@@ -583,14 +598,16 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -1305,10 +1398,12 @@ -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, - u32 ticks); +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); ++ ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -603,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d +@@ -603,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); -- cgit v1.2.3