From 894d50da25d002530d83907f0b5015b76d92e912 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@openwrt.org>
Date: Mon, 16 May 2011 21:50:20 +0000
Subject: kernel: backport some ssb changes to support a mac80211 update

SVN-Revision: 26911
---
 .../942-ssb_commit_settings_export.patch           | 77 ++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch

(limited to 'target/linux/generic/patches-2.6.31')

diff --git a/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch
new file mode 100644
index 0000000000..2bd551233c
--- /dev/null
+++ b/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+ 	pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-				u32 address, u32 data)
+-{
+-	/* This is used for both, PCI and ChipCommon core, so be careful. */
+-	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-	struct ssb_device *dev;
+-
+-	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-	if (WARN_ON(!dev))
+-		return;
+-	/* This forces an update of the cached registers. */
+-	ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+ 				   struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1406,6 +1406,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++				u32 address, u32 data)
++{
++	/* This is used for both, PCI and ChipCommon core, so be careful. */
++	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++	struct ssb_device *dev;
++
++	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++	if (WARN_ON(!dev))
++		return;
++	/* This forces an update of the cached registers. */
++	ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+ 	u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -675,6 +675,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);
-- 
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